Vision system

• US 4,577,344 A
• Filed: 01/17/1983
• Issued: 03/18/1986
• Est. Priority Date: 01/17/1983
• Status: Expired due to Term

• Current Assignee: Acuity Brands, Inc.
• Original Assignee: Automatix, Inc. (Acuity Brands, Inc.)
• Inventors: Warren, Theodore L., Whelan, Kenneth R., Reinhold, Arnold G.
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Mancuso, Joseph
• Application Number:
  US06/458,729
• Time in Patent Office: 1,156 Days
• Field of Search: 382/41, 382/49, 382/54, 382/50, 382/52, 382/53, 382/1, 382/65, 358/107, 358/108, 364/134
• US Class Current: 382/100
• CPC Class Codes: G06T 1/0014 Image feed-back for automatic industrial control, e.g. robot with camera robots B25J19/023

Abstract

A system for sensing, processing and analyzing images includes a camera assembly for sensing a workpiece image and generating video signals representing the sensed images. The video signals are fed through a multiplexer to a vision processor and a display. The video signals are preprocessed and stored in the vision processor which has a shared memory. A computer controller, which has access to the shared memory via a common bus, controls operation of the vision processor in response to command signals from peripheral devices. The controller generates data signals for presenting the sensed images on a display and controlling external devices in response to the visual characteristics of the workpiece.

Claims

1. A system for sensing, processing and analyzing images, said system comprising:

(a) a plurality of camera means for sensing images and generating video signals defining said sensed images;

(b) vision processing means communicating with said camera means for processing said video signals, said vision processing means including at least two central processing units, shared memory means for storing said video signals during all stages of processing of said video signals and internal bus means communicating with each said central processing unit and with said shared memory means;

(c) external bus means communicating with said vision processing means, said external bus means providing communication with at least the shared memory means;

(d) computer controller means communicating with said shared memory means through said external bus means, said computer controller means at least generating command signals for controlling said vision processing means;

(e) display means connected to said computer controller means, selected image signals being presented on said display means; and

,

(f) switch means for selectively switching said video signals generated by said camera means, selected ones of said video signals being applied to said vision processing means and said display means.

2. The system as claimed in claim 1 wherein said video signals generated by said camera means are analog video signals and wherein said vision processing means includes analog-to-digital converter means and level and gain adjusting means, said level and gain adjusting means connected to said switch means and said analog-to-digital converter means, said analog video signals being applied to said level and gain adjusting means from said switch means and then to said analog-to-digital converter means, said analog-to-digital converter means digitizing said analog video signals applied thereto from said level and gain adjusting means.

3. The system as claimed in claim 1 wherein said vision processing means includes a vision processor arbiter with each said central processing unit generating request signals for access to said shared memory means, said request signals being fed to said vision processor arbiter, said vision processor arbiter generating grant signals on a priority basis with access to said shared memory means being controlled by said vision processor arbiter.

4. The system as claimed in claim 3 wherein said vision processor means includes a plurality of holding registers for sequentially storing said digitized video signals, each said holding register holding one byte of video information, said bytes of video information being stored in said shared memory means.

5. The system as claimed in claim 4 wherein said vision processor means includes a plurality of holding buffers, the number of holding buffers corresponding to the number of holding registers, said bytes of video information stored in said shared memory means being fed to said holding buffers and time multiplexed into a single byte.

6. The system as claimed in claim 5 wherein said computer controller means includes a computer controller processor for at least generating command signals for controlling said vision processor means and a computer controlling arbiter for generating request and grant signals in response to address signals generated by said computer controller processor, said computer controller processor having access to said shared memory means through said external bus means.

7. The system as claimed in claim 1 wherein said switch means is a multiplexer having first and second sets of electronic switches, said video signals generated by said camera means fed to said vision processing means through said first set of switches, said video signals generated by said camera means fed to said display means through said second set of switches.

8. A system for image sensing, processing and analyzing, said system comprising:

(a) camera means for sensing images and generating analog video signals defining said sensed images;

(b) multiplexer means communicating with said camera means for selectively switching said analog video signals;

(c) analog-to-digital converter means connected to said multiplexer means, said analog-to-digital converter means digitizing said analog video signals applied thereto from said multiplexer means;

(d) vision processor means connected to said analog-to-digital converter means, said vision processor means processing said digitized signals, said vision processor means including shared memory means for storing said processed digitized signals and at least two central processing units;

(e) internal bus means communicating with said vision processor means, said central processing units communicating with said shared memory means via said internal bus means;

(f) external bus means communicating with said vision processor means, said external bus means providing communication with at least the shared memory means of said vision processor means; and

,

(g) computer controller means communicating with said vision processor means through said external bus means, said computer controller means having access to said shared memory means through said external bus means, said computer controller means generating command signals for controlling said vision processor means.

9. The system as claimed in claim 8 wherein said vision processor means includes computer controlled level adjust means, said analog video signal at an output of said multiplexer means being level adjusted by said level adjust means and variable gain digitized in said analog-to-digital converter means, said digitized signal at an output of said analog-to-digital converter means being a level and gain adjusted digitized video signal.

10. The system as claimed in claim 9 wherein said vision processor means includes a plurality of holding registers for sequentially storing said level adjusted digitized video signals, each said holding register holding one byte of video information, said bytes of video information being stored in said shared memory means.

11. The system as claimed in claim 10 wherein said vision processor means includes a plurality of holding buffers, the number of holding buffers corresponding to the number of holding registers, said bytes of video information stored in said shared memory means being fed to said holding buffers and time multiplexed into a single byte.

12. The system as claimed in claim 11 wherein said vision processor includes a CRT controller for generating address memory signals for storing video information at selected address locations in said shared memory means.

13. The system as claimed in claim 8 wherein said vision processor means includes a vision processor arbiter, each said central processing unit generating request signals for access to said shared memory means, said request signals being fed to said vision processor arbiter, said vision processor arbiter generating grant signals on a priority basis with access to said shared memory means by said central processing units being controlled by said vision processor arbiter.

14. The system as claimed in claim 13 wherein said computer controller means includes a computer controller processor for generating command signals for controlling said vision processor means, said computer controller processor having access to said shared memory through said bus means.

15. The system as claimed in claim 14 wherein said computer controller means includes a computer controller arbiter for generating request and grant signals in response to address signals generated by said computer controller processor, access to said shared memory means by said computer controller means being controlled by said computer controller arbiter.

16. The image and sensing system as claimed in claim 15 including display means, selected ones of said sensed images presented on said display means.

17. The system as claimed in claim 16 wherein said computer controller means includes character generating means for presenting characters on said display means.

18. A system for sensing, processing and analyzing images, said system comprising:

(a) a plurality of camera means for sensing images and generating video signals defining said sensed images; and

,

(b) vision processing means communicating with said camera means for processing said video signals, said vision processing means including;

(i) shared memory means for storing said video signals during all stages of processing of said video signals;

(ii) internal bus means communicating with said shared memory means;

(iii) at least two central processing units; and

,

(iv) a vision processor arbiter;

each said central processing unit communicating with said shared memory means via said internal bus means, each said central processing unit generating request signals for access to said shared memory means, said request signals being fed to said vision processor arbiter, said vision processor arbiter generating grant signals on a priority basis with access to said shared memory means being controlled by said vision processor arbiter.

(c) external bus means communicating with said vision processing means, said external bus means providing communication with at least the shared memory means of said vision processing means;

(d) computer controller means communicating with said shared memory means through said external bus means, said computer controller means at least generating command signals for controlling said vision processing means; and

,

(e) means for utilizing the video signals processed by said vision processing means.

19. A system for image sensing, processing and analyzing, said system comprising:

(a) camera means for sensing images and generating analog video signals defining said sensed images;

(b) multiplexer means communicating with said camera means for selectively switching said analog video signals;

(c) analog-to-digital converter means connected to said multiplexer means, said analog-to-digital converter means digitizing said analog video signals applied thereto from said multiplexer means;

(d) vision processor means communicating with said camera means for processing said video signals, said vision processor means including;

(i) shared memory means for storing said video signals during all stages of processing of said video signals;

(ii) internal bus means communicating with said shared memory means;

(iii) at least two central processing units; and

,

(iv) a vision processor arbiter;

each said central processing unit communicating with said shared memory means via said internal bus means, each said central processing unit generating request signals for access to said shared memory means, said request signals being fed to said vision porcessor arbiter, said vision processor arbiter generating grant signals on a priority basis with access to said shared memory means being controlled by said vision processor arbiter;

(e) external bus means connunicating with said vision processing means, said external bus means providing communication with at least the shared memory means of said vision processing means;

(f) computer controller means communicating with said shared memory means through said external bus means, said computer controller means at least generating command signals for controlling said vision processing means; and

,

(g) means for utilizing the video signals processed by said vision processing means.