Circuit and method for split bias enable/inhibit memory operation

• US 4,578,594 A
• Filed: 01/25/1984
• Issued: 03/25/1986
• Est. Priority Date: 01/25/1984
• Status: Expired due to Fees

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Fairchild Camera and Instrument Corporation
• Inventors: Santos, Joe
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Davis, B. R.
• Application Number:
  US06/573,532
• Time in Patent Office: 790 Days
• Field of Search: 307/240-245, 307/494, 307/498, 328/99
• US Class Current: 327/530
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: H03K 17/615 in a Darlington configuration

Abstract

A circuit and method for enabling/disabling a differential signal output from a memory device, such as a bipolar static random access memory, is disclosed. A split bias, current steering circuit includes a first differential amplifier for steering a current I_D along a first current path when a first selected differential input signal, corresponding to a first logic state, is coupled to a first input terminal of said first differential amplifier; and includes a second differentialamplifier for steering current I_D along a second current path when a second selected differential input signal, corresponding to a second logic state, is coupled to a second input terminal of said second differential amplifier. An output stage produces a selected logic output signal according to which of said first and second current paths is selected to steer current I_D. A split bias enable/inhibit stage provides controlled operation of the first and second differential amplifiers. Circuit operation is inhibited by splitting a bias signal supplied to the differential amplifiers. When inhibited, the circuit steers current I_D along a predetermined one of said first and second current paths. This produces a corresponding continual predetermined logic output signal without regard to the differential input signal present at the first and second input terminals. Circuit operation is enabled by balancing the bias signal supplied to the differential amplifiers. When enabled, both differential amplifiers connected to the output stage are operative.

Claims

1. A circuit for steering a current supplied by a current source to produce a predetermined circuit output signal in response to a selected circuit differential input signal, comprising:

a first differential amplifier, coupled to receive said current, for steering said current along a first current path in response to said selected circuit differential input signal;

a second differential amplifier, coupled to receive said current, for alternatively steering said current along a second current path in response to said selected circuit differential input signal;

output means, coupled to receive said current, for producing said predetermined circuit output signal according to which of said first and second current paths said current is steered; and

means, coupled to said first and second differential amplifiers, for producing a balanced control signal to selectively enable each of said first and second differential amplifiers, whereby said current is steered along a selected one of said first and second current paths in response to said selected circuit differential input signal to produce said predetermined circuit output signal; and

for alternatively producing a split control signal to selectively inhibit each of said first and second differential amplifiers, whereby said current is steered along a predetermined one of said first and second current paths to continually produce a corresponding circuit output signal without regard to said selected circuit differential input signal.

2. A memory enable/inhibit circuit, comprising:

a first differential transistor pair having an input terminal coupled to receive a first logic input signal and being operable to steer a current along a first current path in response thereto, and having a first bias terminal coupled to receive a first portion of a bias signal;

a second differential transistor pair having an input terminal coupled to receive a second logic input signal and being operable to steer said current along a second current path in response thereto, and having a second bias terminal coupled to receive a second portion of said bias signal; and

output means, having a control terminal coupled to a node along said second current path, for producing a first logic output signal when said current is steered along one of said current paths and for producing a second logic output signal when said current is steered along the other of said current paths.

3. The circuit of claim 2, further comprising:

enable/inhibit means, coupled to said first and second bias/enable terminals, for producing said bias signal, wherein circuit operation is enabled when a balanced bias signal is coupled to said first and second bias terminals, and wherein circuit operation is inhibited when a split bias signal is coupled to said first and second bias terminals.

4. The circuit of claim 3, wherein said first differential transistor pair includes:

(a) a first transistor having a first terminal coupled to a current source, a second terminal coupled to a current sink, and a control terminal coupled to receive said first logic input signal; and

(b) a second transistor having a first terminal coupled to said current source, a second terminal coupled to said current sink, and a control terminal coupled to receive said bias signal; and

wherein said second differential transistor pair includes;

(a) a third transistor having a first terminal coupled to said current source, a second terminal coupled to said current sink, and a control terminal coupled to receive said second logic input signal; and

(b) a fourth transistor having a first terminal coupled to said current source, a second terminal coupled to said current sink, and a control terminal coupled to receive said bias signal.

5. The circuit of claim 4, said output means including a fifth transistor coupled between said current source and said second and fourth transistors and having a first terminal coupled to said current source, a control terminal coupled to said second and fourth transistors, and a second terminal coupled to provide said first logic output signal when current is steered along one of said current paths and to provide said second logic output signal when current is steered along the other of said current paths.

6. The circuit of claim 5, said enable/inhibit means including:

a first bias source coupled to said first bias terminal, for providing said first portion of said bias signal thereto;

a second bias source coupled to said second bias terminal, for providing said second portion of said bias signal thereto; and

means, coupled to said first and second bias sources, for selectably operating said bias sources to produce a balanced bias signal when circuit operation is enabled and to produce a split bias signal when circuit operation is inhibited.

7. A memory enable/inhibit circuit, comprising:

a first differential amplifier including;

(a) a first transistor having a first terminal connected to a current source, a second terminal connected to a current sink, and a control terminal coupled to receive a first logic input signal; and

(b) a second transistor having a first terminal coupled to said current source, a second terminal coupled to said current sink, and a control terminal coupled to receive a bias signal;

a second differential amplifier including;

(a) a third transistor having a first terminal coupled to said current source, a second terminal coupled to said current sink, and a control terminal coupled to receive a second logic input signal; and

(b) a fourth transistor, having a first terminal coupled to said current source, a second terminal coupled to said current sink, and a control terminal coupled to receive said bias signal;

an output amplifier, including;

(a) a fifth transistor having a first terminal coupled to said current source, a control terminal coupled to the first terminal of said second and fourth transistors, and a second terminal for producing a first logic output signal in response to said first logic input signal and for producing a second logic output signal in response to said second logic input signal; and

(b) means, coupled between said fifth transistor first terminal and control terminal to produce a control voltage at said transistor control terminal; and

enable/inhibit means, including;

(a) a first bias source coupled to said first bias terminal;

(b) a second bias source coupled to said second bias terminal; and

(c) a differential transistor pair coupled to operate said first and second bias sources to selectably provide a balanced bias signal when circuit operation is enabled and to provide a split bias signal when circuit operation is inhibited.

8. The circuit of claim 7, said first and third transistors being operable to provide a first current path when a first logic signal is coupled to the control terminal of said first transistor;

said second and fourth transistors being operable to provide a second current path when said second logic input signal is coupled to the control terminal of said fourth transistor; and

said fifth transistor being operable to provide a first logic output signal and a second logic output signal corresponding to which of a respective one of said first and second current paths is provided.

9. The circuit of claim 8, said first bias source and said second bias source being coupled to provide a balanced bias signal to said first and second bias terminals to operate said second and third transistors when circuit operation is enabled, and being operable to provide a split bias signal to said first and second bias terminals to select a predetermined one of said first and second current paths, and to produce a corresponding logic output signal without regard to said first and second logic input signals when circuit operation is inhibited.

10. In a memory circuit including a first differential transistor pair having an input terminal coupled to receive a first logic input signal and being operable to steer a current along a first current path in response thereto having a second differential transistor pair having a second input terminal coupled to receive a second logic input signal and being operable to steer a current along said second current path in response thereto, and having an output stage operable to produce a first logic output signal and a second logic output signal in response to the one of said corresponding first and second selected current paths along which current is steered, a method for enabling and disabling circuit operation, comprising:

providing a bias signal to a bias terminal of each differential transistor pairs whereby circuit operation is enabled such that said first and second current paths may readily be selected in response to said corresponding first and second logic input signals; and

providing a split bias signal to said bias terminal, whereby circuit operation is inhibited, such that a predetermined current path is continuously selected without regard to said first and second logic input signals.

11. The method of claim 10, further comprising the steps of:

providing a first component of said bias signal to one of said differential transistor pairs; and

providing a second component of said bias signal which is balanced relative to said first component when circuit operation is enabled and which is split relative to said first component when circuit operation is inhibited.