Method and apparatus for recovering data and clock information from a self-clocking data stream

• US 4,578,799 A
• Filed: 10/05/1983
• Issued: 03/25/1986
• Est. Priority Date: 10/05/1983
• Status: Expired due to Term

• Current Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Original Assignee: Codenoll Technology Corp (TE Connectivity Limited)
• Inventors: Coden, Michael H., Scholl, Frederick W.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/539,128
• Time in Patent Office: 902 Days
• Field of Search: 375/110, 375/8, 375/7, 360/42, 307/269
• US Class Current: 375/333
• CPC Class Codes: G11B 20/1419 to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A method and apparatus are disclosed for recovering data and clock information from high speed self-clocking data streams at rates of up to approximately 50 Mbps. The self-clocking data stream has a predetermined bit period and two voltage levels with negative-going and positive-going voltage level transitions. A pulse is generated for each voltage level transition in the coded stream. This pulse is applied to a non-retriggerable one-shot that produces an output pulse that is approximately the duration of one-half of a bit period. After the output pulse of the one-shot terminates, the one-shot is non-retriggerable for a period of time less than the duration of one-half of a bit period. The output pulse from the one-shot provides clock information derived from the coded bit stream. This clock information is provided to the clock input of a bistable storage device and the coded bit stream is applied to a data input to the storage device. In response to the clock input, the bistable storage device decodes the coded bit stream to provide decoded data information at an output.

Claims

1. In a data transmission system using self-clocking bi-phase coded bit streams, said bit streams having a predetermined bit period and two voltage levels with negative-going and positive-going voltage level transitions occurring in the stream to indicate clock information and data information, at least a first such voltage level transition and possibly a second voltage level transition occurring in each bit period, apparatus for recovering said information comprising:

means for generating from each voltage level transition in the coded bit stream, a pulse having a first polarity,

a non-retriggerable one-shot to which is applied the pulse of first polarity, said one-shot producing an output pulse having a duration that is approximately the time interval between said first and second voltage transitions and being non-retriggerable after said pulse terminates for a period of time less than the difference between the duration of a bit period and the duration of said output pulse, said output pulse providing clock information derived from the coded bit stream, and

bistable storage means having a clock input to which clock information from an output of the one-shot is applied and a data input to which the coded bit stream is applied, said clock information being delayed by less than said time interval relative to any delay experienced by the coded bit stream, said bistable storage means providing at an output thereof data information decoded from the coded bit stream.

2. The apparatus of claim 1 wherein the generating means comprises:

3. The apparatus of claim 1 wherein the generating means comprises:

a first logic gate having a non-inverted output and an inverted output and

first and second means for differentiating signals from said non-inverted output and said inverted output.

4. The apparatus of claim 3 wherein the combining means comprises:

a second logic gate to which is applied the differentiated signal from said non-inverted output,

a third logic gate to which is applied the differentiated signal from said inverted output, and

means for wiring together outputs from the second and third logic gates to form a logical OR.

5. The apparatus of claim 3 wherein the logic gates or OR gates.

6. The apparatus of claim 3 wherein the logic gates are OR gates implemented in emitter coupled logic integrated circuits.

14. The apparatus of claim 1 wherein the bit period is at least 20 nanoseconds, the clock information applied to the clock input of the bistable storage means is delayed by approximately 10 nanoseconds relative to the coded bit stream received at the generating means and the coded bit stream applied to the data input of the bistable storage means is delayed by approximately 2.5 nanoseconds.

15. The apparatus of claim 1 wherein the time interval between said first and second voltage transitions is approximately one-half the bit period.

7. In a data transmission system using self-clocking bi-phase coded bit streams, said bit streams having predetermined bit period and two voltage levels with negative-going and positive-going voltage level transitions occurring in the steam to indicate clock information and data information, at least a first such voltage level transition and possibly a second voltage level transition occuring in each bit period, apparatus for recovering said information comprising:

means for generating from each voltage level transition in the coded bit stream, a pluse having a first polarity,

a non-retriggerably one-shot to which is applied the pulse of first polarity, siad one-shot producing an output pulse having a duration that is approximately the time interval between said first and second voltage transitions and being non-retriggerable after said pulse terminates for a period of time less than the difference between the duration of a bit period and the duration of said output pulse, said output pulse providing clock information derived from the coded bit stream, wherein said one-shot comprises;

a first logic gate having at least two inputs, a first of which is connected to said generating means and received said pulse having a first polarity,

means connected to an output of said first logic gate for generating a ramp signal whose magnitude decreases gradually from a peak value,

a second logic gate connected to said ramp signal generating means for generating said output pulse while the magnitude of said ramp signal exceeds a threshold logic value, and

means for feeding said output pulse back to a second input of the first logic gate to inhibit said gate so that the one-shot cannot be retriggered while said output pulse is present at said second input to the first logic gate, and

bistable storage means having a clock input to which clock information from an output of the one-shot is applied and a data input to which the coded bit stream is applied, said clock information being delayed by less than said time interval relative to any delay experienced by the coded bit stream, said bistable storage means providing at an output thereof data information decoded from the coded bit stream.

8. The apparatus of claim 7 wherein the ramp signal generating means further comprises means for varying the rate at which the magnitude of the ramp signal decreases, whereby the duration of the output pulse is varied.

9. The apparatus of claim 7 wherein the ramp signal generating means is an RC network in which a voltage level is stored in a capacitor that is gradually discharged through a resistor.

10. The apparatus of claim 9 wherein the resistance of said resistor can be varied to vary the rate at which the magnitude of the ramp signal decreases, whereby the duration of the output pulse is varied.

11. The apparatus of claim 7 wherein the means for feeding back the output pulse comprises a delay means.

12. The apparatus of claim 7 wherein the first and second logic gates and the means for feeding back the output pulse are OR gates.

13. The apparatus of claim 7 wherein the first and second logic gates and the means for feeding back the output pulse are OR gates implemented in emitter coupled logic integrated circuits.

16. In a data transmission system using self-clocking bi-phase coded bit streams, said bit streams having a predetermined bit period and two voltage levels with negative-going and positive-going voltage level transitions occurring in the stream to indicate clock information and data information, at least a first such voltage level transition and possibly a second voltage transition occurring in each bit period, a method for recovering said information comprising the steps of:

applying the coded bit stream to a data input to a bistable storage means,

generating from each voltage level transition in the coded bit stream, a pulse having a first polarity,

applying said pulse to a non-retriggerable one-shot to produce an output pulse having a duration that is approximately the time interval between said first and second voltage transitions, said output pulse providing clock information derived from the coded bit stream,

inhibiting said one-shot so that it cannot be retriggered after said pulse terminates for a period of time less than the difference between the duration of a bit period and the duration of said output pulse, and

applying said clock information to a clock input of said bistable storage means to clock said data stream into said bistable storage means, said clock information being delayed by less than said time interval relative to any delay experienced by the coded bit stream, said bistable storage means providing at an output thereof data information decoded from the coded bit stream.

17. The method of claim 16 wherein the generating step comprises the steps of:

generating complementary edges from each voltage level transition in the coded bit stream and

combining the complementary edges to produce a pulse having a first polarity.

19. The method of claim 16 wherein the bit period is at least 20 nanoseconds, the clock information applied to the clock input of the bistable storage means is delayed by approximately 10 nanoseconds relative to the coded bit stream received at the generating means and the coded bit stream applied to the data input of the bistable storage means is delayed by approximately 2.5 nanoseconds.

20. The method of claim 16 wherein the time interval between said first and second voltage transitions is approximately one-half the bit period.

18. In a data transmission system using self-clocking bi-phase coded bit streams, said bit streams having a predetermined bit period and two voltage levels with negative-going and positive-going voltage level transitions occuring in the stream to indicate clock information and data information, at least a first such voltage level transition and possibly a second voltage transition occurring in each bit period, a method for recovering said information comprising the steps of:

applying the coded bit stream to a data input to a bistable storage means,

generating from each voltage level transition in the coded bit stream, a pulse having a first polarity,

applying said pulse to a non-retriggerably one-shot to produce an output pulse having a duration that is approximately the time interval between said first and second voltage transitions, said output pulse providing clock information derived from the coded bit stream, wherein said one-shot comprises;

a first logic gate having at least two inputs, a first of which is connected to said generating means and receives said pulse having a first polarity,

means connected to an output of said first logic gate for generating a ramp signal whose magnitude decreases gradually from a peak value, and

a second logic gate connected to said ramp signal generating means for generating said output pulse while the magnitude of said ramp signal exceeds a threshold logic value,

inhibiting said one-shot so that it cannot be retriggered after said pulse terminates for a period of time less than the difference between the duration of a bit period and the duration of said output pulse, said step of inhibiting the one-shot comprising the step of feeding said output pulse back to a second input of the first logic to inhibit said gate so that the one-shot cannot be retriggered while said output pulse is present at said second input to the first logic gate, and

applying said clock information to a clock input of said bistable storage means to clock said data stream into said bistable storage means, said clock information being delayed by less than said time interval relative to any delay experienced by the coded bit stream, said bistable storage means providing at an output thereof data information decoded from the coded bit stream.

21. The method of claim 18 wherein the generating step comprises the steps of:

generating complementary edges from each voltage level transition in the coded bit stream and

combining the complementary edges to produce a pulse having a first polarity.

22. The method of claim 18 wherein the bit period is at least 20 nanoseconds, the clock information applied to the clock input of the bistable means in delayed by approximately 10 nanoseconds relative to the coded bit stream received at the generating means and the coded bit stream applied to the data input of the bistable storage means is delayed by approximately 2.5 nanoseconds.