Soft-starting phase-control circuit for low voltage load

• US 4,580,088 A
• Filed: 02/29/1984
• Issued: 04/01/1986
• Est. Priority Date: 02/29/1984
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Bloomer, Milton D.
• Primary Examiner(s): Beha, Jr., William H.
• Application Number:
  US06/584,705
• Time in Patent Office: 762 Days
• Field of Search: 323/238, 323/242, 323/243, 323/245, 323/321, 363/49
• US Class Current: 323/238
• CPC Class Codes: H02M 5/293 using semiconductor devices only
• CPC Class Codes: H05B 39/048 with reverse phase control
• CPC Class Codes: Y02B 20/00 Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps

Abstract

A soft-starting phase-control circuit for controlling both the cold in-rush and normal operating flows of current through a load from an A.C. source. The load may be resistive, may have a non-zero resistance temperature coefficient and may require a load voltage thereacross lower than the voltage provided by the A.C. source connected to the load and the control circuit. The control circuit utilizes at least one power switching device for selectively enabling and disabling the connection between source and load responsive to turn-on and turn-off states of a control signal provided at the output of a gate subcircuit. The gate subcircuit provides a turn-on state at a time, after each zero crossing, variably responsive to either a sensed load parameter when the load is in the normal operating condition, or to a selected starting sequence each time the load is initially energized (either intentionally or responsive to recovery from a detected fault condition) to limit in-rush current to a relatively low multiple of the normal operating current. The start-up sequence of load turn-on states is responsive to gate enabling signals provided by comparison of a reference level with the instantaneous magnitude of a ramped signal, itself terminated and restarted at each line zero crossing. Only if a phase-locked loop has been synchronized to the source line voltage zero crossings can the gate means be driven to the turn-on state. The exact time when the ramp signal reaches the reference level is controlled by integration of the sum of the outputs of selected ones of a plurality of current sources.

Claims

1. A circuit for phase-controlling both the starting and normal operating flows of current from an A.C. source to a load, comprising:

power switching means for selectively respectively enabling and disabling a connection of said source to said load, responsive to respective first and second states of a control signal;

means for generating at least one signal having a transition in a selected direction occurring substantially at each of a sequential plurality of zero crossings of the source signal waveform and for also providing a lock signal only if said at least one signal selected transition occurs essentially at each sequential one of said source signal waveform zero crossings;

means for generating a ramp signal commencing at a first magnitude responsive to the selected transition of each of said at least one signal and reaching a second magnitude, greater than said first magnitude, by the occurrence of the selected transition of the next successive one of said at least one signal;

means for providing said first control signal state responsive to the instantaneous magnitude of said ramp signal exceeding a predetermined magnitude and for thereafter providing said second control signal state responsive to the selected transition of the next successive one of said at least one signal;

first means, responsive to the presence of said lock signal, for controlling the slope of said ramp signal to increase the second magnitude thereof over a plurality of time intervals each between successive ones of the selected transition of said at least one pulse signal, from a magnitude less than said predetermined magnitude to a magnitude greater than said predetermined magnitude, to cause said power switching means to enable a starting load current flow increasing from a substantially zero initial magnitude toward a magnitude greater than the desired normal operating magnitude;

second means, monitoring a selected parameter of said load, for controlling the slope of said ramp signal to cause said second magnitude to vary responsive to the sensed load parameter; and

switching means for enabling said first means to control said ramp signal slope until said sensed load parameter approaches a preselected value thereof and for then switching control of said ramp signal slope to said second means for controlling the duration of current flow during each source waveform cycle thereafter to cause said load current flow to maintain substantially the said preselected value of said sensed load parameter.

2. The circuit of claim 1, wherein said ramp signal generating means comprises:

an integrating element across which said ramp signal is formed by integration of the sum of all source signals presented thereto;

first signal source means for providing a first source signal to said integration element; and

means for resetting the magnitude of the signal across said integrating element to said first magnitude responsive to each selected transition.

3. The circuit of claim 2, wherein said ramp signal generating means resets the ramp signal magnitude to a substantially-constant first magnitude at said occurrence of said selected transition;

and said first source provides a substantially-constant magnitude signal.

4. The circuit of claim 2, wherein said first source signal is of a magnitude insufficient to increase the ramp signal second magnitude to exceed said predetermined magnitude prior to the resetting of said integrating element signal.

5. The circuit of claim 4, wherein said integrating element is an integration capacitance.

6. The circuit of claim 5, wherein said first signal source is a substantially-constant current source.

7. The circuit of claim 2, wherein said resetting means comprises a switching device having an input and a controlled-conduction circuit coupled across said integrating element and controlled to a conductive condition responsive to each occurrence of said at least one signal selected transition at said input.

8. The circuit of claim 2, wherein said control signal state providing means comprises:

means for providing a first condition if the integrated signal is less than said predetermined magnitude and for providing a second condition if said integrated signal is greater than said predetermined magnitude; and

means for generating the control signal respective connection-enabling first state and connection-disabling second state responsive respectively to said first and second conditions.

9. The circuit of claim 8, wherein said condition providing means comprises:

means for generating a reference signal of said predetermined magnitude; and

means for comparing the reference signal magnitude to the instantaneous magnitude of said ramp signal for providing said first and second conditions respectively responsive to said ramp signal magnitude being less than or greater than said reference signal magnitude.

10. The circuit of claim 9, wherein the control signal controlling means includes means for controlling at least one of the turn-on and turn-off characteractics of said power switching means.

11. The circuit of claim 2, wherein said first means comprises:

means responsive to at least said lock signal for providing, only if said lock signal is present, a second source signal of substantially monotonically-increasing magnitude to said integrating element over said plurality of time intervals.

12. The circuit of claim 11, further comprising means for disconnecting said second source signal from said integrating element responsive to said switching means switching control of said ramp signal slope to said second means.

13. The circuit of claim 12, wherein said integrating element is an integration capacitance;

and said second signal providing means is a means for providing a variable current of magnitude increasing over said plurality of time intervals.

14. The circuit of claim 13, wherein said variable current source means comprises:

a voltage-controlled current source having a control input and an output at which a controlled second current appears responsive to the magnitude of the voltage at said input; and

means for providing to said control input a voltage having a magnitude sufficient to provide a substantially zero magnitude current from said second current source at least prior to the occurrence of said lock signal and for thereafter changing the control input voltage in a direction to substantially monotonically increase the controlled-source output second current to said integrating element.

15. The circuit of claim 14, wherein said control input voltage-providing means comprises:

a timing network having a plurality of elements establishing the current source control input voltage responsive to a flow of a third current through said network;

means for providing a substantially-constant third current flow through said network only after said lock signal is provided; and

means cooperating with said network for assuring that said current source control input voltage is of a magnitude preventing a flow of said second current prior to enablement of said third current source by said lock signal.

16. The circuit of claim 11, wherein said first means is set to control the magnitude of the starting load current to never exceed a predetermined maximum magnitude.

17. The circuit of claim 2, wherein said second means comprises:

means for providing a fourth current of variable magnitude responsive to at least the magnitude of the sensed load parameter; and

means for respectively disabling and enabling said fourth current from being introduced into said integrating means responsive to said first means being respectively enabled and disabled, after the occurrence of said lock signal.

18. The circuit of claim 17, wherein said fourth current source is a voltage-controlled current source having a control input and an output at which said fourth current is provided with a magnitude responsive to the voltage at said control input;

and further including;

sensor means for monitoring the magnitude of said selected load parameter to provide a sensor output signal; and

means for converting said sensor output signal to a voltage signal at said fourth current source control input.

19. The circuit of claim 18, wherein said load is a resistive load and said sensed load parameter is the temperature of said load.

20. The circuit of claim 19, wherein said sensor comprises:

sensing means adjacent to said load for providing a sensor resistance of magnitude varying responsive to said load resistance temperature; and

said converting means comprises bridge amplifier means for converting the sensor resistance magnitude to the magnitude of the voltage at said fourth current source means control input.

21. The circuit of claim 20, wherein said bridge amplifier means includes means for adjusting said fourth current source input voltage to a predetermined nominal value responsive to the actual sensor resistance at a predetermined temperature.

22. The circuit of claim 17, further comprising means for setting the maximum instantaneous magnitude of said fourth current to establish a maximum normal load current magnitude.

23. The circuit of claim 17, wherein said first means comprises:

means responsive to at least said lock signal for providing, only if said lock signal is present, a second source signal if substantially monotonically-increasing magnitude over said plurality of time intervals to said integrating element.

24. The circuit of claim 23, wherein said switching means comprises:

first means for generating a first signal responsive to the magnitude of said second source current;

means for generating a second signal responsive to the sensed load parameter;

means comparing said first and second generated signals for providing respective first and second conditions responsive to said first generated signal being respectively greater than and less than said sensed-load-parameter second generated signal; and

means responsive to said comparing means respective first and second conditions for respectively enabling and disabling said first means and respectively disabling and enabling said second means to control said ramp signal slope.

25. The circuit of claim 24, wherein said first signal generating means comprises:

means for providing a voltage responsive substantially only to the varying magnitude of said second current;

said second signal generating means comprises means for generating a voltage responsive substantially only to the varying magnitude of said fourth current responsive to said sensed load parameter; and

said comparing means comprises a voltage comparator having first and second inputs each coupled to receive an associated one of said first and second generated voltages and an output providing a signal having said first and second conditions dependent upon the relative magnitude of the voltages connected to the comparator inputs.

26. The circuit of claim 25, wherein said control means comprises a flip-flop logic element controlled by at least said comparator output signal.

27. The circuit of claim 1, wherein said at least one signal and lock signal generating means comprises:

means for detecting zero crossings of said source signal waveform to provide selected-direction transitions of one of said at least one signal; and

phase-locked loop (PLL) means receiving said zero-crossing detecting means output signal transitions for generating at a PLL means output one of said at least one signal having transitions in said desired direction and for also generating said lock signal when said PLL means output signal transitions occur essentially at each sequential one of said source signal waveform zero crossings.

28. The circuit of claim 1, wherein said power switching means includes at least one insulated gate transistor.