Semiconductor device of non-single crystal structure

• US 4,581,620 A
• Filed: 06/29/1981
• Issued: 04/08/1986
• Est. Priority Date: 06/30/1980
• Status: Expired

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Shunpei Yamazaki
• Inventors: Yamazaki, Shunpei, Nagata, Yujiro
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): Jackson, Jerome
• Application Number:
  US06/278,418
• Time in Patent Office: 1,744 Days
• Field of Search: 357/2, 357/30 J, 357/30 K, 357/30, 357/58, 357/16, 357/91, 357/20, 357/59
• US Class Current: 257/53
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7866 Non-monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 31/046 PV modules composed of a plurality of thin film solar cells deposited on the same substrate
• CPC Class Codes: H01L 31/0465 comprising particular structures for the electrical interconnection of adjacent PV cells in the module H01L31/0463 takes precedence
• CPC Class Codes: H01L 31/202 including only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 148/077 : Implantation of silicon on sapphire
• CPC Class Codes: Y10S 148/093 : Laser beam treatment in general

Abstract

A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semi-conductor region formed primarily of semi-amorphous semiconductor. The second semi-conductor region has a higher degree of conductivity than the first semiconductor region so that a semi-conductor element may be formed.

Claims

1. A semiconductor device comprising:

a substrate and

a non-single crystal semiconductor layer formed on or over the substrate, the non-single crystal semiconductor layer being composed of a first semiconductor region formed primarily of a first semi-amorphous semiconductor and a second semiconductor region (a) formed primarily of a second semi-amorphous semiconductor containing microcrystalline semiconductor more than the first semi-amorphous semiconductor and (b) having a higher degree of conductivity than the first semiconductor region;

wherein the first and second semiconductor regions are laterally arranged side by side on or over the substrate.

2. A semiconductor device according to claim 1, which further comprises a first conductive layer extending between the substrate and the second semiconductor region and a second conductive layer extending on or over the second semiconductor region.

3. A semiconductor device according to claim 2 which further comprises a first insulating layer extending between the first conductive layer and the second semiconductor region and a second insulating layer extending between the second semiconductor region and the second conductive layer.

4. A semiconductor device according to claim 1, wherein the second semiconductor region is doped with an impurity which imparts thereto an N or P conductivity type.

5. A semiconductor device according to claim 1 where said non-single crystal semiconductor layer is further composed of a third semiconductor region (a) formed primarily of said second semi-amorphous semiconductor and where the first, second and third semiconductor regions are laterally arranged side by side on or over the substrate so that first semiconductor region is sandwiched between the second and third semiconductor regions.

6. A semiconductor device according to claim 5 wherein the second and third semiconductor regions are doped with an impurity which imparts thereto an N or P conductivity type.

7. A semiconductor device according to claim 6 further comprises an insulating layer extending on the first semiconductor region and a conductive layer extending on the insulating layer.

8. A semiconductor device according to claim 1 where said non-single crystal semiconductor layer is composed of a plurality of said first semiconductor regions where each is formed primarily of said first semi-amorphous semiconductor and a plurality of said second semiconductor regions where each is formed primarily of said second semi-amorphous semiconductor and where the first and second semiconductor regions are laterally arranged side by side on or over the substrate.

9. A semiconductor device according to claim 8 which further comprises a first conductive layer extending between the substrate and the non-single-crystal semiconductor layer.

10. A semiconductor device comprising:

a plurality of photoelectric conversion elements formed on a substrate side by side;

wherein the photoelectric conversion elements each has a first conductive layer as a first electrode formed on the substrate, a non-single-crystal semiconductor layer formed on the first conductive layer, formed of Si, Ge, Si3N_4-x (0<

x<

4), SiO_2x (0<

x<

2) or Si_x Ge_1-x (0<

x<

1), or a material consisting principally thereof and doped with hydrogen or halogen as a dangling bond neutralizer, and a second conductive layer as a second electrode formed on the non-single-crystal semiconductor layer;

wherein the second conductive layer of one of the photoelectric conversion elements is coupled with the first conductive layer of the next photoelectric conversion element;

wherein the non-single-crystal semiconductor layers of the photoelectric conversion elements each has a first semiconductor region and a second semiconductor region having a higher degree of conductivity than the first semiconductor region;

wherein the first and second semiconductor regions are laterally arranged side by side on the first conductive layer; and

wherein the first semiconductor region is formed primarily of a first semiamorphous semiconductor, and wherein the second semiconductor region is formed primarily of a second semiamamorphous semiconductor containing more microcrystalline semiconductor than the first semiamorphous semiconductor.

11. A semiconductor device according to claim 10, which further comprises a first insulating layer extending between the first conductive layer and the second semiconductor region and a second insulating layer extending between the second semiconductor region and the second conductive layer.

12. A semiconductor device according to claim 10, wherein the second semiconductor region is doped with an impurity which imparts thereto an N or P conductive type.

13. A semiconductor device comprising:

a plurality of MIS type transistors formed side by side on a substrate;

wherein the MIS type transistors each has a non-single-crystal semiconductor layer formed on the substrate an insulating layer formed on the non-single-crystal semiconductor layer and a conductive layer formed on the insulating layer;

wherein the non-single crystal semiconductor layer is formed of Si, Ge, Si₃ N_4-x (0<

x<

4), SiO_2-x (0<

x<

2), SiC_x (0<

x<

1) or Si_x Ge_1-x (0<

x<

1), or a material consisting principally thereof and doped with hydrogen or halogen as a dangling bond neutralizer;

wherein the non-single-crystal semiconductor has a first semiconductor region as a channel region a second and third semiconductor regions as a source and drain regions respectively connected with the opposing sides of the first semiconductor regions, respectively and having a P or N conductivity type and having a higher degree of conductivity than the first region;

wherein the third, first and second regions are laterally arranged side by side in this order on the substrate;

wherein the insulating layer is disposed on at least the first semiconductor region as a gate insulating layer;

wherein the conductive layer is disposed on at least the first semiconductor region through the insulating layer as a gate electrode; and

wherein the first semiconductor region is formed primarily of a first semi-amorphous semiconductor, and wherein the second and third semiconductor regions are formed primarily of a second semi-amorphous semiconductor containing more microcrystalline semiconductor than the first semi-amorphous semiconductor.