Video display apparatus

• US 4,581,655 A
• Filed: 03/30/1984
• Issued: 04/08/1986
• Est. Priority Date: 03/31/1983
• Status: Expired due to Fees

• Current Assignee: Toshiba Denzai Kabushiki Kaisha
• Original Assignee: Toshiba Denzai Kabushiki Kaisha
• Inventors: Ide, Katsuyuki, Hamaguchi, Mitsuhiro, Shibano, Nobuo
• Primary Examiner(s): Masinick, Michael A.
• Assistant Examiner(s): Toth, E. Anne
• Application Number:
  US06/595,532
• Time in Patent Office: 739 Days
• Field of Search: 358/242, 358/241, 358/163
• US Class Current: 348/798
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2320/0285 using tables for spatial correction of display data
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: H04N 3/12 by switched stationary formation of lamps, photocells or light relays

Abstract

In a picture image display apparatus including a large number of display elements which are lighted by digitalized level adjusted light data produced by a video signal, the digitalized level adjusted light data are corrected by the difference between a mean quantity of light and the light quantity of each luminous element so as to light the luminous element during an interval corresponding to the level adjusted light data without using any light quantity adjusting circuit.

Claims

1. Video display apparatus comprising:

a display device including a plurality of luminous elements arranged to form a display surface;

image signal generating means outputting digitalized level adjusted light data as image signals for respective luminous elements;

a first memory device for storing said level adjusted light data of at least one picture displayed in a subsequent time period by said display device;

a second memory device for storing values obtained by converting differences between a mean light quantity of respective luminous elements when they are supplied with a predetermined operating power and a light quantity of each luminous element into level differences of said level adjusted light data;

an arithmetic operation circuit for correcting the level adjusted light data stored in said first memory device with data stored in said second memory device and then outputting corrected level adjusted light data;

display control means for lighting said luminous elements for intervals corresponding to said corrected level adjusted light data outputted from said arithmetic operation circuit.

2. The video display apparatus according to claim 1 wherein said signal generating means produces said digitalized level adjusted light data from a video signal received by an antenna or reproduced from a video tape recorder.

3. The video display apparatus according to claim 1 wherein said arithmetic operation circuit comprises an addition/subtraction circuit supplied with a level adjusted light data read out from said first memory device and light quantity correction data read out from said second memory device for producing a shift up signal, a shift down signal and a signal representing result of addition or subtraction, an OR gate circuit inputted with said shift up signal and said signal representing result of addition or subtraction, and an AND gate circuit inputted with an output of said OR gate circuit and a signal produced by inverting said shift down signal.

4. The video display apparatus according to claim 1 wherein said arithmetic operation circuit comprises a multiplier supplied with a multiplying constant of less than one or larger than 1 as light quantity correction data from said second memory device and said level adjusted light data read out from said first memory device so as to produce a shift up signal and a signal representing result of multiplication, and an OR gate circuit inputted with said shift up signal and said signal representing result of multiplication.