Active matrix assembly for a liquid crystal display device including an insulated-gate-transistor

• US 4,582,395 A
• Filed: 07/30/1981
• Issued: 04/15/1986
• Est. Priority Date: 07/31/1980
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Suwa Seikosha
• Original Assignee: Kabushiki Kaisha Suwa Seikosha
• Inventors: Morozumi, Shinji
• Primary Examiner(s): Corbin, John K.
• Assistant Examiner(s): Lewis, David
• Application Number:
  US06/288,605
• Time in Patent Office: 1,720 Days
• Field of Search: 350/334, 350/333, 350/332, 340/784, 340/765, 357/23 TF, 357/7, 365/220, 365/240, 307/481, 307/482, 307/578, 307/279, 377/79
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components

Abstract

An active matrix assembly for a liquid crystal display device utilizing an MIS (metal-insulator-semiconductor) transistor array is provided. The active matrix assembly includes a transparent substrate, a first thin layer of silicon disposed thereon, an insulating film on the first silicon layer and a second thin layer of silicon disposed on the insulating film. The layers are selectively etched for forming a gate and the silicon layers are doped for forming a MOS transistor for a display element of the device. The two silicon layers and insulating material intersect to form capacitors with the upper electrode of the storage capacitor being the driving electrode for the liquid crystal. An active matrix assembly constructed and arranged in accordance with the invention permits 90 percent or more of incident light coming from above to pass therethrough. Use of such a transparent substrate in an active matrix liquid crystal display device permits utilization of a transparent liquid crystal drive, such as the field effect type liquid crystal for providing a maximum degree of contrast. Operation of the device with peripheral drive circuits for the gate lines and data lines including non-inverting rationless shift registers formed in the same manner as the active matrix permits a substantial reduction in power consumption due to reduced parasitic capacitance.

Claims

1. An active matrix assembly for a liquid crystal display device including a plurality of liquid crystal display elements and associated drive circuit components in the matrix arranged in columns and rows, comprising:

a transparent substrate selected from the group consisting of glass, soda glass, high melting point glass and quartz;

a first thin film of silicon selectively deposited on said substrate;

an insulation film deposited on said first film of silicon; and

a second thin film of silicon selectively deposited on said first insulation film;

one of said first and second films of silicon defining one of a source, channel and drain region of a metal-oxide-semiconductor transistor and a gate of said transistor, said transistor coupled to an associated display element for driving said display element.

2. The active matrix assembly of claim 1, wherein said first silicon film defines the source, channel and drain regions of said transistor and the second silicon film defines the gate of the transistor.

3. The active matrix assembly of claim 2, wherein said first silicon film for defining the source, channel and drain regions of the transistor is formed as a non-doped layer.

4. The active matrix assembly of claim 3, wherein said source and drain regions of the transistor are formed by doping impurities into said first silicon film using the gate as a mask.

5. The active matrix assembly of claim 2, further including a second insulation film deposited on said second film of silicon and a wiring material selectively deposited on said second insulation film, said second insulation film defining a dielectric film in the region between said second film of silicon and said wiring material for defining a charge-holding capacitor for an associated display element.

6. The active matrix assembly of claim 1, wherein said first silicon film defines the gate of the transistor and the second silicon film defines the source, channel and drain regions of the transistor.

7. The active matrix assembly of claim 1, wherein said first insulation film defines a dielectric film and said first and second films of silicon define electrodes of a storage capacitor coupled to the junction between each said transistor and the associated display element.

8. The active matrix assembly of claim 1, wherein each said silicon film has a thickness of about 3,700 Å

, or less.

9. The active matrix assembly of claim 1, further including a transparent liquid crystal driving electrode carried by said transparent substrate and coupled to an associated transistor.

10. The active matrix assembly of claim 9, including a wiring material for defining a data line deposited on said substrate, said transparent liquid crystal driving electrode and said wiring material both being formed of the same material.

11. The active matrix assembly of claim 10, wherein said transparent driving electrode is formed from a material selected from the group consisting of an indium and tin oxide transparent conductive film, a metal film having a thickness of about 500 Å

or less, or a thin film of silicon.

12. The active matrix assembly of claims 1 or 9, further including a transparent plate for forming a liquid crystal display panel and a liquid crystal material driveable in the field effect mode disposed between said matrix assembly and said transparent plate.

13. The active matrix assembly of claims 1 or 9, further including peripheral drive circuits on said substrate including non-inverting ratioless shift registers for applying signals to said transistor.

14. The active matrix assembly of claim 1, wherein said matrix includes a plurality of spaced address lines defining a first axis of said matrix and a plurality of spaced data lines intersecting said address lines and defining a second axis of said matrix, said address and data lines being carried by said substrate, each of said transistors having its gate coupled to an address line and its source-drain path coupled to an intersecting data line.

15. The active matrix assembly of claim 14, including address shift register means having an input for receiving a start pulse and a plurality of outputs respectively coupled to said address line, said address shift register further including a plurality of shift register cells, each shift register cell including an input coupled to said address shift register input or to the output of the next proceeding cell, first and second clock inputs for receiving out of phase clock signals and an output for couplinhg to the next cell and to the associated address line, each said cell including transfer transistor means connected at its source-drain path between the cell input and a junction and its drain to one of said clock inputs, an operating transistor coupled at its gate to said junction and its source-drain path between the second clock input and the output, a bootstrap capacitor coupled between said junction and the second clock input, and means for discharging said bootstrap capacitor to terminate the output signal to the associated address line.

16. The active matrix assembly of claim 15, wherein said discharging means includes a discharging transistor having its source-drain path coupled between said output and ground and having its base coupled to said first clock input.

17. The active matrix assembly of claims 15 or 16, wherein said means includes a second discharging transistor having its source-drain path coupled between said output and ground and its gate coupled to the output of a later shift register cell in said address shift register.

18. The active matrix assembly of claim 15, wherein said address shift register is integrated on said substrate simultaneous with the formation of said first-mentioned transistors.

19. The active matrix assembly of claims 14 or 15, including a data shift register including start pulse input means, a data writing buss, a plurality of out of phase clock inputs and a plurality of data shift register cells associated respectively with each of the data lines, each said data shift register cell including an input, an operatiave transistor having its source-drain path coupled between one of said clock inputs and a junction and its gate coupled to the input, said input being coupled to either the start pulse input means or the junction of the prior data shift register cell, a bootstrap capacitor coupled between said input and the associated clock input, means for discharging said bootstrap capacitor when desired, and a sampling and hold transistor coupled at its gate to said junction and with its source-drain path between said data writing buss and the associated data line.

20. The active matrix assembly of claim 19, wherein said discharging means of said data shift register including a discharging transistor coupled with its source-drain path between the associated junction and ground and having its gate coupled to the junction of a later data shift register cell in said data shift register.

21. The active matrix assembly of claim 19, wherein said data shift register includes a reset input, each of said data shift register cells including a further short circuiting transistor coupled with its source-drain path between the associated junction and ground and with its gate connected to said reset input.

22. The active matrix assembly of claim 19, wherein said data shift register is integrated on said substrate simultaneous with the formation of first-mentioned transistors.

23. A liquid crystal display device including an active matrix assembly having a plurality of liquid crystal display elements and associated drive circuit components in matrix array, comprising:

a transparent substrate;

a first thin film of silicon deposited on said transparent substrate, said first film of silicon selectively formed to define one of a transistor gate and a transistor source, channel and gate coupled to each said display element;

an insulation film deposited on said first film of silicon for defining the gate insulation film for said transistor;

a second film of silicon deposited on said first insulation film, said second silicon layer being selectively formed and doped to define the other of the transistor gate and the transistor source, channel and drain;

conductive means carried by said substrate and electically coupled to the source-drain path of each said transistor for defining the liquid crystal drive electrode for each said display element;

a first polarizer plate disposed adjacent to said transparent substrate;

a reflection plate disposed adjacent to said first polarizer plate;

a transparent plate having common transparent electrode means disposed on the interior surface thereof, said transparent plate placed opposite to and spaced apart from said matrix array for forming a space therebetween;

a second polarizer disposed on the exterior surface of said transparent plate; and

a liquid crystal material in the space formed between said matrix array and the transparent plate.

24. The liquid crystal display of claim 23, wherein said liquid crystal material is a twisted nematic liquid crystal material adapted to be driven in the field effect mode.

25. The liquid crystal display device of claim 23, wherein said first and second films of silicon define the electrode of a storage capacitor associated with each display element, said first insulation film deposited therebetween defining a dielectric material for said storage capacitor, one of the electrodes of said storage capacitor being coupled to the junction between the source-drain path of the associated transistor and the liquid crystal drive electrode for the associated liquid crystal display element.

26. The liquid crystal display device of claim 25, and including a ground line formed of a conductive material carried by said substrate, said capacitor being coupled between said junction and said ground line.

27. The liquid crystal displays device of claim 23, wherein said matrix includes a plurality of spaced address lines defining a first axis of said matrix and a plurality of spaced data lines intersecting said address lines and defining a second axis of said matrix, said address and data lines being carried by said substrate, each of said transistors having its gate coupled to an address line and its source-drain path coupled to an intersecting data line.

28. The liquid crystal display device of claim 27, including address shift register means having an input for receiving a start pulse and a plurality of outputs respectively coupled to sadi address line, said address shift register further including a plurality of shift register cells, each shift register cell including an input coupled to said address shift register input or to the output of the next proceeding cell, first and second clock inputs for receiving out of phase clock signals and an output for coupling to the next cell and to the associated address line, each said cell including transfer transistor means connected at its source-drain path between the cell input and a junction and its drain to one of said clock inputs, an operating transistor coupled at its gate to said junction and its source-drain path between the second clock input and the output, a bootstrap capacitor coupled between said junction and the second clock input, and means for discharging said bootstrap capacitor to terminate the output signal to the associated address line.

29. The liquid crystal display of claim 28, wherein said discharging means includes a discharging transistor having its source-drain path coupled between said output and ground and having its base coupled to said first clock input.

30. The liquid crystal display device of claims 28 or 29, wherein said discharging means includes a second discharging transistor having its source-drain path coupled between said output and ground and its gate coupled to the output of a later shift register cell in said address shift register.

31. The liquid crystal display device of claims 27 or 28, including a data shift register including start pulse input means, a data writing buss, a plurality of out of phase clock inputs and a plurality of data shift register cells associated respectively with each of the data lines, each said data shift register cell including an input, an operative transistor having its source-drain path coupled between one of said clock inputs and a junction and its gate coupled to the input, said input being coupled to either the start pulse input means or the junction of the prior data shift register cell, a bootstrap capacitor coupled between said input and the associated clock input, means for discharging said bootstrap capacitor when desired, and a sampling and hold transistor coupled at its gate to said junction and with its source-drain path between said data writing bus and the associated data line.

32. The liquid crystal display device of claim 31, wherein said discharging means of said data shift register including a short circuiting transistor coupled with its source-drain path between the associated junction and ground and having its gate coupled to the junction of a later data shift register cell in said data shift register.

33. The liquid crystal display device of claim 31, wherein said data shift register includes a reset input, each of said data shift register cells including a further short circuiting transistor coupled with its source-drain path between the associated junction and ground and with its gate connected to said reset input.

34. The liquid crystal display device of claim 28, wherein said address shift register is intergated on said substrate simultaneous with the foremation of said first-mentioned transistors.

35. The liquid crystal display device of claim 31, wherein said data shift register is integrated on said substrate simultaneous with the formation of first-mentioned transistors.

36. An active matrix assembly for a liquid crystal display device including a plurality of liquid crystal display elements and associated drive circuit components in the matrix arranged in columns and rows, comprising:

a transparent substrate selected from the group consisting of glass, soda glass, high melting point glass and quartz;

a first thin film of silicon selectively deposited on said substrate for defining a source, channel and drain region of a metal-oxide-semiconductor transistor associated with each display element;

an insulation film deposited on said first film of silicon; and

a second film of silicon selectively deposited on said first insulation film defining a gate of said transistor and one electrode of a storage capacitor associated with said transistor.

37. The active matrix assembly of claim 36, wherein said second silicon film defines the lower electrode of said storage capacitor.

38. The active matrix assembly of claim 36, wherein the first silicon film defines the lower electrode of the storage capacitor and the insulation film defines a dielectric film of said capacitor and said second silicon film defines the upper electrode of the capacitor and the driving electrode.

39. The active matrix assembly of claim 36, wherein each said silicon film has a thickness of about 3,700 Å

, or less.

40. The active matrix assembly of claim 36, wherein said first silicon film is deposited as a non-doped layer.

41. The active matrix assembly of claim 40, wherein said source and drain regions are formed by doping impurities into said first silicon film utilizing the gate as a mask.

42. An active matrix assembly for a liquid crystal display device including a plurality of liquid crystal display elements and associated drive circuit components in the matrix arranged in columns and rows, comprising:

a transparent substrate selected from the group consisting of glass, soda glass, high melting point glass and quartz;

a first thin film of silicon selectively deposited on said substrate;

an insulation film deposited on said first film of silicon;

a second thin film of silicon selectively deposited on said first insulation film;

one of said first and second films of silicon defining one of a source, channel and drain region of a metal-oxide-semiconductor transistor and a gate of said transistor, said transistor coupled to an associated display element for driving said display element; and

a transparent conductive wiring material deposited for forming spaced data lines and an array of transparent driving electrodes, each of said driving electrodes coupled to an associated transistor.

43. The active matrix assembly of claim 42, wherein said transparent conductive wiring is selected from the group consisting of an indium and tin oxide transparent conductive film, a metal film having a thickness of about 500 Å

or less, or a thin film of silicon.

44. The active matrix assembly of claim 42, wherein each said silicon film has a thickness of about 3,700 Å

, or less.

45. An active matrix assembly for a liquid crystal display device including a plurality of liquid crystal display elements and associated drive circuit components in the matrix arranged in columns and rows, each of said display elements comprisng:

a transparent substrate selected from the group consisting of glass, soda glass, high-melting point glass or quartz;

a thin film of silicon selectively deposited on said substrate for defining a source, channel and drain region of a metal-oxide-semiconductor transistor;

a gate insulation film on said film of silicon;

a gate on said gate insulation film; and

a thin film of a transparent conductive material selectively deposited on said substrate for defining an associated liquid crystal driving electrode coupled to said transistor.

46. The active matrix assembly of claim 45, wherein the thin film of silicon is one of polycrystalline silicon or amorphous silicon.

47. The active matrix assembly of claim 45, wherein the transparent conductive material is one of an indium and tin oxide, tin oxide or aluminum.

48. An active matrix assembly for a liquid crystal display device including a plurality of liquid crystal display elements and associated drive circuit components in the matrix arranged in columns and rows, comprising:

a transparent substrate selected from the group consisting of glass, soda glass, high-melting point glass or quartz;

a thin film of silicon selectively deposited on said substrate for defining a source, channel and drain region of a metal-oxide-semiconductor transistor associated with each display element in the matrix;

a gate insulation film on said thin film of silicon;

a gate on said gate insulation film; and

a transparent conductive material film selectively deposited on said substrate for defining spaced gate lines and gates of said transistors and a matrix of associated liquid crystal driving electrodes, each driving electrode coupled to associated transistor.

49. The active matrix assembly of claim 48, wherein said picture element electrodes are formed of a thin film of indium and tin oxide, tin oxide and aliminum.

50. The active matrix assembly of claim 48, wherein the thin film silicon is one of polycrystalline silicon or amorphous silicon.

51. An active matrix assembly for a liquid crystal display device including a plurality of liquid crystal display elements and associated drive circuit components in the matrix arranged in columns and rows, comprising:

a transparent substrate selected from the group consisting of glass, soda glass, high-melting point glass or quartz;

a thin film of silicon selectively deposited on said substrate for defining a source, channel and drain region of a metal-oxide-semiconductor transistor associated with each display element in the matrix;

a gate insulation film on said thin film of silicon;

a gate on said gate insulation film; and

a transparent conductive film selectively deposited on said substrate for defining gates of said transistors and one electrode of a storage capacitor associated with each said transistor.

52. The active matrix assembly of claim 51, wherein said thin film of silicon is one of polycrystalline silicon or amorphous silicon.

53. The active matrix assembly of claim 51, wherein said transparent conductive film is one of indium and tin oxide, tin oxide or aluminum.