Fault tolerable redundancy control

• US 4,583,224 A
• Filed: 11/07/1983
• Issued: 04/15/1986
• Est. Priority Date: 11/08/1982
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ishii, Kazuhiko, Noguchi, Atomi, Gotoh, Yoshimi
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/549,435
• Time in Patent Office: 890 Days
• Field of Search: 371/16, 371/36, 371/11, 371/67, 371/68
• US Class Current: 714/10
• CPC Class Codes: G05B 9/03 with multiple-channel loop, i.e. redundant control systems
• CPC Class Codes: G06F 11/184 where the redundant components implement processing functionality
• CPC Class Codes: G06F 11/185 and the voting is itself performed redundantly
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability

Abstract

A redundant control system in which three output signals from three equivalent signal processors are compared with each other to judge whether each of the output signals is normal or abnormal, an abnormal output signal thus determined is replaced by a set signal having a predetermined level, and then a majority operation is performed for normal output signals and the set signal to obtain a control signal. The control signal is formed of the logical product or logical sum of two normal output signals according as the predetermined level of the set signal is "1" or "0". In the case where a circuit for generating the above-mentioned control signal are formed in triplicate and a majority operation is performed for three control signals, a fault occurring at other circuit portions than a majority logic circuit at the final stage is permissible. Further, the reliability of the control system is enhanced by forming abnormality detecting means in triplicate and performing a majority operation for the outputs of three abnormality detecting means.

Claims

1. A redundant control system in which a plurality of equivalent control signals from a plurality of equivalent signal processors are subjected to majority logic operation, to deliver a system control signal, said redundant control system comprising:

at least three equivalent signal processors connected in parallel for receiving an information signal and for generating respective control signals which will be identical to one another when the processors are operating without fault;

error detecting means connected to receive said control signals from said signal processor for comparing each of said control signals with each of the other control signals to check for the presence of an abnormal control signal which is different in level from that of the majority of the control signals and to generate an error detection signal on an output line corresponding to said different control signal;

means for generating a set signal which represents a mode of control upon occurrence of a fault in at least one of said signal processors;

swithcing means connected to receive said control signals from said signal processors, any error detection signal generated by said error detection means and said set signal for transmitting control signals which are not accompanied by a corresponding error detection signal and for replacing said control signal accompanied by an error detection signal with said set signal; and

a majority logic circuit connected to receive the outputs of said switching means for performing a majority logic operation among the outputs of said switching means to generate a system control signal.

2. A redundant control system according to claim 1, further comprising a latch circuit for latching the output of said error detecting means, and a masking circuit for preventing said latch circuit from generating an output signal, during a predetermined time period.

3. A redundant control system according to claim 2, further comprising a diagnosing circuit connected to receive the outputs of said switching means and the output of said majority logic circuit for performing a majority logic operation for the outputs of said switching means and for comparing the result of said majority logic operation with the output of said majority logic circuit, to deliver a logic fault signal when the result of said majority logic operation is different from the output of said majority logic circuit.

4. A redundant control system according to claim 1, wherein said switching means includes NOR means connected to receive said control signals and said error detection signal to perform a NOR logic operation on each of the control signals and a corresponding detection signal, AND means connected to receive said error detection signal and said set signal to perform an AND logic operation on each of the detection signal and the set signal, and NOR means connected to receive the output of each one of said NOR means and the output of a corresponding one of said AND means to perform a NOR logic operation.

5. A redundant control system according to claim 4, wherein said AND means includes a series combination of an NAND gate and an inverter.

6. A redundant control system according to claim 1, wherein said error detection signal is applied to said switching means through said signal processor.

7. A redundant control system according to claim 1, further comprising display means for displaying the presence of a fault in accordance with the output of said error detecting circuit.

8. A redundant control system according to claim 1, further comprising equivalent sensors of the same function each supplying an output thereof to a corresponding one of said signal processors to cause said signal processors to deliver said control signals on the basis of the outputs of said sensors.

9. A redundant control system in which three ON-OFF control signals from threee equivalent processors are subjected to a majority logic operation to deliver a majority control signal, said redundant control system comprising:

three equivalent processors connected in parallel for receiving a common information signal and for generating respective ON-OFF control signals which would be identical to one another when the processors are operating without fault;

error detecting means connected to said equivalent processors to receive said control signals for comparing each said control signal with each of the other control signals to detect an abnormal control signal which is different from other control signals and for generating three changeover signals corresponding respectively to said control signals, each of which changeover signals is in an ON state when the associated control signal is abnormal and in an OFF state when the associated control signal is normal;

means for generating a set signal which is preselected to be in an ON or OFF state according to a desired mode of control when a fault occurs in at least one of said processors;

three switching circuits, each of said switching circuits being connected to receive said control signals, said three changeover signals and said set signal and operating to generate three output signals, each output signal of a respective switching circuit being equal to a corresponding one of said control signals when a corresponding one of said changeover signals is in the OFF-state and for converting an ouptut signal into a signal determined by the ON or OFF state of said set signal when the changeover signal corresponding to said output signal is in the ON-state;

three first majority logic circuits corresponding to said switching circuits, each of said first majority logic circuits being connected to receive three outputs from a corresponding one of said switching circuits, to perform a majority logic operation; and

a second majority logic circuit connected to receive three outputs from said first majority logic circuits for performing a majority operation to deliver said majority control signal.

10. A redundant control system according to claim 9, said error detecting means including three error detecting circuits corresponding to said switching circuits, each of said error detecting circuits being applied with three output signals from a corresponding one of said switching circuits for putting one of said output signals in the ON-state and putting the remaining output signals in the OFF-state when said one output signal is different in level from the remaining output signals, and three third majority logic circuits corresponding to said control signals, each of said third majority logic circuits being applied with three output signals delivered from said error detecting circuits and corresponding to one of said control signals, for performing a majority operation to detect an error signal from said control signals on the basis of the outputs of said third majority logic circuits.

11. A redundant control system according to claim 10, said errors detecting means further including first latch circuits, each of said first latch circuits being connected between one of said error detecting circuits and said third majority logic circuits for preventing output signals of the error detecting circuit from being applied to said third majority logic circuits, during a predetermined masking time period, to get rid of a transient error signal from the error detecting circuit due to the asynchronism of three output signals of a corresponding switching circuit.

12. A redundant control system according to claim 9, further comprising three diagnosing circuits corresponding to said first majority logic circuits, each of said diagnosing circuits being applied with three output signals of a corresponding one of said switching circuits for performing a majority logic operation to diagnose a corresponding one of said first majority logic circuits on the basis of the comparison between the result of said majority logic operation and the output of said corresponding first majority logic circuit, and a fourth majority logic circuit applied with three output signals from said three diagnosing circuits for performing a majority logic operation to diagnose said third majority logic circuits on the basis of the output of said fourth majority logic circuit.

13. A redundant control system according to claim 12, further comprising second latch circuits, each of said second latch circuits being connected between one of said diagnosing circuits and said fourth majority logic circuit for preventing the output signal of a corresponding one of said diagnosing circuits from being applied to said fourth majority logic circuit, during a predetermined masking time period, to get rid of a transient erroneous output from the diagnosing circuit due to the asynchronism of three output signals of a corresponding switching circuit.