Digital demodulator arrangement for quadrature signals

• US 4,583,239 A
• Filed: 10/18/1984
• Issued: 04/15/1986
• Est. Priority Date: 10/29/1983
• Status: Expired due to Fees

• Current Assignee: STC PLC (f/k/a Standard Telephones and Cables)
• Original Assignee: STC PLC (f/k/a Standard Telephones and Cables)
• Inventors: Vance, Ian A. W.
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US06/662,050
• Time in Patent Office: 544 Days
• Field of Search: 375/39, 375/80, 375/94, 375/23, 375/86, 375/77, 455/60, 455/324, 329/107
• US Class Current: 375/324
• CPC Class Codes: H03D 2200/005 Analog to digital conversion
• CPC Class Codes: H03D 2200/0052 Digital to analog conversion
• CPC Class Codes: H03D 3/006 by sampling the oscillations and further processing the samples, e.g. by computing techniques H03D3/007 takes precedence
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence
• CPC Class Codes: H04L 27/1525 using quadrature demodulation
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits

Abstract

A direct conversion receiver in which the quadrature I and Q signals are converted into pulse density modulated digital data streams by delta-sigma modulators 14, 15. The resultant digital data streams are then processed in a logic block 18 according to predetermined logic truth tables. The digital output of the processor 18 is then converted back to an analogue signal.

Claims

1. A direct conversion radio receiver comprising means for receiving a modulated carrier frequency signal and for converting the signal to in-phase and quadrature-phase baseband signals;

a pair of analog-to-digital conversion means connected to said receiving means for converting the in-phase and quadrature-phase signals into respective pulse density modulated (PDM) digital data streams; and

logic means coupled to said pair of conversion means and responsive to said pulse density modulated digital data streams for providing a demodulated output signal.

2. A receiver according to claim 1 wherein each analogue-to-digital conversion means comprises a delta-sigma modulator.

3. A receiver according to claim 1 wherein the logic means includes look-up table means addressed by the digital data and combinational logic coupled to said look-up table means wherein the output of the look-up table means is a binary weighted digital word defining values of an analogue signal represented by the digital signals.

4. A method of demodulating a pair of related in-phase and quadrature-phase signals provided by a zero I.F. or direct conversion radio receiver comprising analog-to-digital converting each of said in-phase and quadrature-phase signals into respective pulse density modulated (PDM) digital data streams;

and logically processing said pulse density modulated digital data streams in accordance with a predetermined table of input logic conditions to provide a demodulated output signal.