Method and apparatus for demodulating a carrier wave which is phase modulated by a subcarrier wave which is phase shift modulated by baseband signals

• US 4,584,534 A
• Filed: 09/06/1983
• Issued: 04/22/1986
• Est. Priority Date: 09/09/1982
• Status: Expired due to Fees

• Current Assignee: Agence Spatiale Europeenne
• Original Assignee: Agence Spatiale Europeenne
• Inventors: Lijphart, Enno E., Drewes, Gerardus
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Pascal, Robert J.
• Application Number:
  US06/529,632
• Time in Patent Office: 959 Days
• Field of Search: 329/110, 329/112, 329/120, 329/122, 375/53, 375/56, 375/83, 375/84, 455/205, 455/208
• US Class Current: 329/308
• CPC Class Codes: H04B 14/08 characterised by the use of a sub-carrier

Abstract

The invention relates to a method for demodulating a carrier wave which is phase modulated by a subcarrier wave which is phase shift modulated by baseband signals and applies especially to data transmission between a spacecraft and a ground station. The technological problem addressed is reduction of signal degradation and, consequently, of transmission power and size of the receiving antenna. According to the invention, the frequency is first down converted to an intermediate frequency (f_c) which is lower than the carrier wave frequency; the subcarrier wave is extracted by phase demodulation using a Costas loop; digital sampling is performed on the signal demodulated in a Costas loop at a frequency which is twice the intermediate frequency (f_c) and the bit clock frequency (f_B) is regenerated in a first order phase locked loop using the subcarrier wave frequency as a reference frequency.

Claims

1. A method for demodulating a carrier wave which is phase modulated by a subcarrier wave which is phase shift modulated by baseband signals, according to which at least one phase demodulation process is performed using a Costas tracking loop to regenerate the carrier wave, wherein the baseband signals obtained are all subsequently sampled, then decoded, characterized by the fact that a carrier wave frequency is first converted to an intermediate frequency which is lower than the carrier wave frequency, that the subcarrier wave is extracted by a phase demodulation process using a modified Costas loop having a digital circuit portion comprising a waveform synthesizer by which the subcarrier is regenerated and matched digital filters, that digital sampling is then performed on the signal demodulated in said modified Costas loop at a frequency which is twice the frequency of the intermediate frequency and that a bit clock frequency is regenerated in a first order phase locked loop wherein the subcarrier wave frequency is used as a reference frequency in regeneration of said bit clock frequency.

2. A method as claimed in claim 1, characterized by the fact that the bit clock frequency is obtained by phase determination in a first order phase locked loop in which a matched digital signal is multiplied at the end of each bit by a matched signal at midbit, wherein the subcarrier frequency is divided by the resulting signal to produce the bit clock frequency.

3. A method as claiemd in either claim 1 or claim 2, characterized by the fact that the level of an input signal of the modified Costas loop is regulated as a function of an output digital signal.

4. A method as claimed in claim 2, characterized by the fact that a signal matched in phase to a signal of said bit clock frequency is integrated in such a way as to produce a signal which indicates occurrence of bitslip.

5. A method as claimed in any of claims 1, 2, and 4, characterized by the fact that a waveform at the carrier wave frequency supplied by the waveform synthesizer is matched to an input signal waveform at said intermediate frequency as modified by characteristics of a demodulator mixer circuit.

6. A method as claimed in any of claims 1, 2, and 4 characterized by the fact that a digital baseband output signal sampled at an end of each of a clock pulse bit is squared and added to a sum of squares, in such a way as to compute a probability of bit errors.

7. A method as claimed in any of claims 1, 2, and 4 characterized by the fact that subcarrier demodulation is omitted and by the fact that carrier demodulation is achieved by sampling the signal at a frequency which is equal to four times the intermediate frequency, so as to demodulate signals modulated by binary phase shift keying.

8. An apparatus for implementing a process for demodulating a carrier wave which is phase modulated by a subcarrier wave which is phase shift modulated by baseband signals, by which at least one phase demodulation process is performed using a Costas tracking loop to regenerate the carrier wave, wherein the baseband signals obtained are all subsequently sampled, then decoded, wherein a carrier wave frequency is first converted to an intermediate frequency which is lower than the carrier wave frequency, and the subcarrier wave is extracted by a phase demodulation process using a modified Costas loop, characterized by the fact that each "data" arm and "error" arm of the modified Costas loop comprises, in sequence, a demodulator mixer circuit which receives a waveform at subcarrier wave frequency, a bandpass filter, a sampling multiplier which receives a signal at a frequency which is twice the intermediate frequency, an analog to digital converter and a matched digital filter controlled by the bit clock frequency and the output of which is received by a multiplier of "data" and "error" arm signals.

9. An apparatus as claimed in claim 8, characterized by the fact that the central branch of the modified Costas loop comprises, sequentially and starting from a multiplier of "data" and "error" arm signals, a second order loop filter, a variable frequency oscillator, and a waveform synthesizer which is driven by the bit clock frequency and connected to the two demodulator mixer circuits by a digital to analog converter.

10. An apparatus as claimed in claim 9, characterized by the fact that the waveform synthesizer comprises two digital memories in each of which one waveform cycle is stored.

11. An apparatus as claimed in any of claims 8 through 10, and further comprising a second order phase locked loop which receives the input signal at intermediate frequency and supplies a signal the frequency of which is a multiple of the intermediate frequency.

12. An apparatus as claimed in any of claims 8 through 10, and further comprising a variable attenuator positioned at the input of the modified Costas loop and controlled by a digital circuit similar to an RC analog filter and supplying an average value of output bit signals.

13. An apparatus as claimed in any of claims 8 through 10, characterized by the fact that the first order phase locked loop which regenerates the bit clock frequency comprises two arms, each of which comprises a matched digital filter controlled by the bit clock frequency, wherein one of said filters is the filter of the "data" arm of the modified Costas loop and the other of said filters is controlled by a wave in opposed phase with respect to a wave controlling the "data" arm filter of the modified Costas loop.

14. An apparatus as claimed in claim 13, characterized by the fact that the matched digital filters of the modified Costas loop and of the clock frequency regeneration loop consist of sum-into-register modules.

15. An apparatus for implementing a process for demodulating a carrier wave which is phase modulated by a subcarrier wave which is phase shift modulated by baseband signals, by which at least one phase demodulation process is performed using a Costas tracking loop to regenerate the carrier wave, wherein the baseband signals obtained are all subsequently sampled, then decoded, wherein a carrier wave frequency is first converted to an intermediate frequency which is lower than the carrier wave frequency, and the subcarrier wave is extracted by a phase demodulation process using a modified Costas loop, and comprising at least one processor of a bit slice type which executes at least some digital functions of the process, wherein functional analog processes are executed in technology known as integrated function technology.

16. An apparatus as claimed in claim 15, wherein the processor comprises a microprocessor, and high speed digital functions are executed separately in integrated circuit technology with a very high degree of integration.