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Digital PLL decoder

  • US 4,584,695 A
  • Filed: 11/09/1983
  • Issued: 04/22/1986
  • Est. Priority Date: 11/09/1983
  • Status: Expired due to Fees
First Claim
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1. A digital phase lock loop circuit comprising:

  • a serial data input line for supplying received data signals;

    a driver clock generator having multiple output terminals at which the generator provides clock signals having a predetermined phase relationship to each other;

    a driver clock line alternately connectable to any one of the terminals;

    input sampling means responsive to signals on said driver clock line to take samples of data bit signals received on said data input line, to detect sample the patterns; and

    commutator means connected by a respective line to each of the clock generator terminals, and responsive to an UP/DOWN signal to connect the driver clock line to a determined one of the terminals.

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