Digital PLL decoder
First Claim
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1. A digital phase lock loop circuit comprising:
- a serial data input line for supplying received data signals;
a driver clock generator having multiple output terminals at which the generator provides clock signals having a predetermined phase relationship to each other;
a driver clock line alternately connectable to any one of the terminals;
input sampling means responsive to signals on said driver clock line to take samples of data bit signals received on said data input line, to detect sample the patterns; and
commutator means connected by a respective line to each of the clock generator terminals, and responsive to an UP/DOWN signal to connect the driver clock line to a determined one of the terminals.
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Abstract
A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.
113 Citations
14 Claims
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1. A digital phase lock loop circuit comprising:
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a serial data input line for supplying received data signals; a driver clock generator having multiple output terminals at which the generator provides clock signals having a predetermined phase relationship to each other; a driver clock line alternately connectable to any one of the terminals; input sampling means responsive to signals on said driver clock line to take samples of data bit signals received on said data input line, to detect sample the patterns; and commutator means connected by a respective line to each of the clock generator terminals, and responsive to an UP/DOWN signal to connect the driver clock line to a determined one of the terminals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A phase lock loop method for detecting clock signal bit edges, comprising the steps of:
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providing a multiple phase driver clock generator producing, at respective terminals, N clock signals phase-offset from each other by 360°
/N;providing a driver clock line connectable to any one of the N terminals, and commutator means responsive to a received signal sample pattern to connect the driver clock line to one of the N terminals instead of another of the N terminals; sampling three times for a received clock signal edge in response to driver clock signals; applying a signal indicating the sample pattern to the commutator; and using the commutator to connect the driver clock line to a terminal for a lagging phase clock signal if the first and second samples in the pattern agree, or to a terminal for a leading phase clock signal if the second and third samples agree. - View Dependent Claims (13, 14)
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Specification