Semiconductor memory redundant element identification circuit
First Claim
1. In a semiconductor integrated circuit having at least one redundant circuit element for substitution for an original circuit element, a test circuit comprising:
- means for indicating at an external pin of the semiconductor integrated circuit whether a redundant circuit element has been substituted for an original circuit element.
2 Assignments
0 Petitions
Accused Products
Abstract
A test circuit (10) for a semiconductor memory is provided. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).
24 Citations
20 Claims
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1. In a semiconductor integrated circuit having at least one redundant circuit element for substitution for an original circuit element, a test circuit comprising:
means for indicating at an external pin of the semiconductor integrated circuit whether a redundant circuit element has been substituted for an original circuit element.
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2. In a semiconductor integrated circuit having at least one redundant circuit element for substitution for an original circuit element, a test circuit comprising:
means for indicating at an external pin of the semiconductor integrated circuit whether a redundant circuit element has been substituted for an original circuit element when the original circuit element is addressed. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9)
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10. A test circuit for a semiconductor memory integrated circuit having at least one redundant circuit element, the redundant circuit element being programmable to replace a defective circuit element, the memory being addressed with address signals and further having a redundant decoder programmed in accordance with the address of a defective circuit element for selecting a redundant circuit element and generating an output signal, the memory having external pins, comprising:
means for indicating the selection of a redundant circuit element on an exteral pin of the semiconductor memory integrated circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A test circuit for a semiconductor memory integrated circuit having at least one redundant circuit element, the redundant circuit element being programmed to replace a defective circuit element, the memory being addressed with address signals and further having a redundant decoder programmed in accordance with the address of a defective circuit element for selecting a redundant circuit element, the memory having external pins, comprising:
means connected to the decoder for indicating the selection of a redundant circuit element on an external pin of the semiconductor memory circuit.
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19. In a semiconductor memory integrated circuit having a plurality of original circuit elements and a plurality of redundant circuit elements for substitution for ones of the plurality of original circuit elements and the memory receiving address signals and having an external pin, a test circuit comprising:
means for indicating at the external pin whether one of the plurality of redundant circuit elements has been substituted for a defective one of the plurality of original circuit elements when the defective one of the plurality of original circuit elements is addressed. - View Dependent Claims (20)
Specification