Microprocessor reset with power level detection and watchdog timer

• US 4,586,179 A
• Filed: 12/09/1983
• Issued: 04/29/1986
• Est. Priority Date: 12/09/1983
• Status: Expired due to Fees

• Current Assignee: Zenith Radio Corporation (LG Corporation)
• Original Assignee: Zenith Electronics Corporation (LG Corporation)
• Inventors: Sirazi, Semir, Zinger, Thomas E.
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/560,086
• Time in Patent Office: 872 Days
• Field of Search: 371/66, 371/62, 371/12, 371/5, 328/140, 328/141, 364/200, 364/900, 364/482
• US Class Current: 714/22
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A combination watchdog timer and input voltage level detector circuit is coupled to a microcomputer (or microprocessor) for insuring proper operation thereof under various conditions. The watchdog timer is coupled to the microcomputer and is responsive to a status signal output by the microcomputer indicating the operating state thereof. Failure of the watchdog circuit to detect the status signal indicates that the microcomputer has become unstable or is in a locked up condition and causes the watchdog circuit to initiate a microcomputer reset by means of a reset trigger circuit. A voltage level detector is coupled to the input voltage source and to the reset trigger circuit for similarly initiating the resetting of the microcomputer in the event the input voltage to the microcomputer drops below a predetermined value. When power is initially applied, a power up detector coupled between the voltage level detector and the watchdog timer ensures that the reset trigger circuit maintains the microcomputer in a reset condition until the input voltage reaches a predetermined level to permit normal microcomputer operation. The present invention thus ensures that the microcomputer is maintained or is placed in a reset condition in the event of input power transients, upon initial application of power to the microcomputer, and upon the occurrence of irregularities in microcomputer program execution.

Claims

1. A system for controlling the operation of signal processing means, said signal processing means energized by an input voltage and including a programmed memory having a plurality of addressable locations wherein are stored instruction words which define operating sequences and further including logic means coupled to said programmed memory for accessing said plurality of addressable locations for sequentially executing said instruction words in generating a status signal in the form of a single, periodic, continuous pulse train in accordance with said operating sequences during normal operation of said signal processing means, said signal processing means responsive to a reset command provided thereto for maintaining said signal processing means in a reset condition wherein said logic means accesses an initialization addressable location in said programmed memory in setting the execution of the programmed instruction words to a predetermined initial point in said operating sequences from which a predetermined sequence of initializing operations is automatically initiated, said system comprising:

voltage level detection means responsive to said input voltage for generating a first signal when said input voltage does not exceed a predetermined voltage level and a second signal when said input voltage exceeds said predetermined voltage level;

first signal detection means coupled to said signal processing means and responsive to the absence of said status signal and further coupled to said voltage level detection means and responsive to receipt of said first signal for generating a single third signal of predetermined duration, said first signal detection means including a single first timing circuit for generating said single third signal when a pulse is not received from said signal processing means within a predetermined time interval of receipt of an immediately preceding pulse; and

second signal detection means coupled to said signal processing means, to said voltage level detection means and to said first signal detection means and responsive to said second and single third signals respectively output therefrom for immediately providing a reset command of said predetermined duration to said signal processing means when said input voltage does not exceed said predetermined voltage level or when said status signal is no longer output by said signal processing means for maintaining the signal processing means in the reset condition for said predetermined duration prior to application of an input voltage greater than said predetermined voltage level thereto.

2. A system as in claim 1 wherein said first signal detection means further includes a second timing circuit having a characteristic RC time constant equal to the predetermined duration of said single third signal for the generation thereof.

3. A system as in claim 2 wherein the single first timing circuit and the second timing circuit of said first signal detection means respectively comprise first and second triggerable self-oscillating circuits which are coupled together and are respectively responsive to said status signal and to said first signal.

4. A system as in claim 3 wherein said first and second triggerable self-oscillating circuits respectively comprise first and second one-shot monostable multivibrators having first and second time constants respectively associated therewith.

5. A system as in claim 4 wherein said system further includes power up detector means coupling said voltage level detection means to said first signal detection means and responsive to said first signal for providing a clear input to said one-shot monostable multivibrators in initiating the output of said single third signal therefrom.

6. A system as in claim 1 wherein said reset command is an active low signal and said second signal detection means includes means for maintaining a reset input of said signal processing means in a high state in the absence of said reset command.

7. A system as in claim 6 wherein said reset input of the signal processing means is maintained in a high state in the absence of said reset command by means of said input voltage provided to said second signal detection means.

8. A system for resetting a microprocessor to an initialization point in the operating program thereof in response to an input voltage interrupt, improper execution of said operating program by said microprocessor, or the application of an input voltage to said microprocessor, wherein said microprocessor generates a timed output signal in the form of a single periodic, continuous, pulse train representing normal execution of said operating program by said microprocessor and said microprocessor is responsive to a reset signal provided thereto in initiating a reset condition in the operation thereof whereby said microprocessor is reset to said initialization point in the operation thereof and wherein said microprocessor is maintained in said reset condition for a predetermined period prior to application of an input voltage equal to or greater than a predetermined voltage level, said system comprising:

first means for detecting said input voltage, for comparing said input voltage to said predetermined voltage level, and for generating a first signal when said input voltage is less than said predetermined voltage level;

signal detection means coupled to said first means and responsive to said first signal output therefrom when said input voltage is less than said predetermined voltage level for generating a single time delayed second signal relative to receipt by said signal detection means of said first signal wherein the time delay of said single second signal is equal to or greater than said predetermined period, said signal detection means further coupled to said microprocessor and including a single timing circuit responsive to the absence of said timed output signal from said microprocessor for generating said single time delayed second signal when a pulse is not received from said microprocessor within a predetermined time interval of receipt of an immediately preceding pulse; and

reset signal means coupled to said microprocessor and to said first means and responsive to said first signal output therefrom for immediately providing a reset signal to said microprocessor when said input voltage is less than said predetermined voltage level, said reset signal means further coupled to said signal detection means and responsive to said single time delayed second signal therefrom for immediately providing said reset signal to said microprocessor upon detection by said single timing circuit of the absence of said time output signal therefrom indicating improper operation of said microprocessor and for maintaining said microprocessor in said reset condition for said predetermined period prior to application of an input voltage equal to or greater than said predetermined voltage level to said microprocessor to ensure the proper resetting thereof.