Asynchronous to synchronous data interface

• US 4,586,189 A
• Filed: 02/16/1984
• Issued: 04/29/1986
• Est. Priority Date: 02/16/1984
• Status: Expired due to Fees

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: ITT Corporation (ITT, Inc.)
• Inventors: Tyrrell, Raymond E.
• Primary Examiner(s): Ng, Jin F.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/580,905
• Time in Patent Office: 803 Days
• Field of Search: 375/106, 375/109, 375/110, 375/112, 375/117, 370/41, 370/48
• US Class Current: 375/370
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
• CPC Class Codes: H04L 5/24 with start-stop synchronous converters

Abstract

A generalized data interface for transmission of asynchronous data from a transmitting terminal to a receiving terminal at a different transmission rate is described. In accordance with the present invention, the high data transmission rates normally associated with synchronous transmission are achievable between asynchronous data terminals using novel asynchronous to synchronous and synchronous to asynchronous converters.

Claims

1. A data transmission system comprising:

a source of asynchronous data at a source clock rate for transmission of a serial bit stream of characters including start/stop bits to a remote destination of asynchronous data;

asynchronous to synchronous data conversion means for alinging the asynchronous data at the source clock rate to a synchronous clock at a different rate for serial synchronous transmission wherein said start/stop bits are extracted and reinserted prior to transmission to said remote asynchronous destination such that no data characters are lost in the data stream including said start/stop bits wherein said means includes a UART (Universal Asynchronous Receiver/Transmit) for performing a baud rate conversion and a clock alignment; and

synchronous to asynchronous data conversion means for coupling said synchronously clocked data stream asynchronously at a desired transmission rate to said remote destination of asynchronous data;

wherein the asynchronous transmission rate is substantially equal to or lower than the synchronous data transmission rate.

2. A data transmission system in accordance with claim 1

wherein said asynchronous to synchronous conversion means includes:

realignment circuit means for sensing an internally generated clock and synchronizing the source clock to a selected internally generated clock only when said internally generated clock is selected, and means for inhibiting transmission of characters until said clocks are aligned.

3. A data transmission system in accordance with claim 2 further including:

FIFO memory means for storing current data characters during realignment to prevent loss of data.

4. In a data transmission system for the synchronous transmission of asynchronous data to an asynchronous data receiver;

a source of asynchronous data at a source clock rate for transmission of a serial bit stream of characters including start/stop bits to said asynchronous data receiver; and

asynchronous to synchronous data conversion means for aligning the asynchronous data at the source clock rate to a synchronous clock at a different rate for serial synchronous transmission wherein said start/stop bits are extracted and reinserted prior to transmission to said asynchronous data receiver such that no data characters are lost in the data stream which at said receiver including said start/stop bits and wherein said conversion means includes a UART (Universal Asynchronous Receive/Transmit) for performing a baud rate conversion and a clock alignment;

wherein said system is adapted so that the asynchronous data transmission rate is lower than or is substantially equal to the synchronous data transmission rate.

5. In a data transmission system in accordance with claim 4 wherein said asynchronous to synchronous data conversion means further includes:

realignment circuit means for sensing an internally generated clock and synchronizing the source clock to a selected internally generated clock only when said internally generated clock is selected, and means for inhibiting transmission of characters until said clocks are aligned.

6. In a data transmission system in accordance with claim 5, further including:

FIFO memory means for storing current data characters during realignment to prevent loss of data.