Evaluation arrangement for a digital incremental transmitter

• US 4,587,485 A
• Filed: 08/02/1983
• Issued: 05/06/1986
• Est. Priority Date: 08/27/1982
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Papiernik, Wolfgang
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Solis, Jose M.
• Application Number:
  US06/519,579
• Time in Patent Office: 1,008 Days
• Field of Search: 364/565, 364/729, 364/559, 250/231 SE, 324/163, 324/160, 324/165, 324/166, 324/167, 324/175, 340/870
• US Class Current: 324/166
• CPC Class Codes: G01D 5/24409 Interpolation using memories
• CPC Class Codes: H03M 1/203 using an analogue interpolation circuit
• CPC Class Codes: H03M 1/303 Circuits or methods for processing the quadrature signals

Abstract

An evaluation arrangement for a digital incremental transmitter of the type wherein two phase-shifted sinusoidal voltages of the same period are produced generates a periodic triangular voltage signal which is subsequently converted to digital values. The digital values are produced in response to an interlinking of linear portions of the sinusoidal voltages. The digital values are used to address a read-only memory in which are stored a plurality of absolute values within a period.

Claims

1. An evaluation arrangement for a digital incremental transmitter of the type having first and second transmitter outputs for producing respective sinusoidal voltages of equal amplitude which are shifted in phase by 90°

with respect to one another, the evaluation arrangement further having a converter for converting the sinusoidal voltages of the first and second transmitter outputs into a measurement signal corresponding proportionally to the count of the periods of the sinusoidal voltages produced, the evaluation arrangement further comprising;

means for producing a periodic triangular voltage having a fundamental frequency which is an integral multiple of the frequency of the sinusoidal voltages in response to an interlinking of linear portions of the sinusoidal voltages;

converter means for converting said triangular voltage into corresponding digital values;

logic means for producing digital logic signals which are derived from the sinusoidal voltages and whose state combinations correspond one to one to the circular segments of the sinusoidal voltages within a period; and

memory means for storing a plurality of corresponding absolute values of the sinusoidal voltages within a period, said memory means having an output for producing selected one of said absolute values and an input for receiving said digital values and said digital logic signals, said absolute values being selected in response to said digital values and said digital logic signals so as to establish the actual position value within a period of the sinusoidal voltages.

2. The evaluation arrangement of claim 1 wherein said means for producing a periodic triangular voltage comprises absolute value forming means for producing absolute value signals corresponding respectively to the sinusoidal voltages;

and

selector means for selecting the smaller of said absolute value signals.

3. The evaluation arrangement of claim 1 wherein there is further provided sampling means connected to said output of said memory means for determining a velocity.

4. The evaluation arrangement of claim 2 wherein said selector means comprises a voltage discriminator for selecting one of said absolute value signals.

5. The evaluation arrangement of claim 1 wherein the digital incremental transmitter is an optical incremental transmitter having a lamp for generating light, the evaluation arrangement further comprising comparator means for comparing a value of said triangular voltage against a reference value and controlling responsively a current flowing through the lamp.

6. The evaluation arrangement of claim 2 wherein there is further provided means for monitoring amplitudes or phase disturbances by producing a trouble signal responsive to a comparison of the larger of said absolute value signals against a reference value.