Interface method and apparatus

• US 4,587,514 A
• Filed: 09/07/1984
• Issued: 05/06/1986
• Est. Priority Date: 09/07/1984
• Status: Expired due to Fees

• Current Assignee: Verilink Corporation (ExeLED Holdings, Inc.)
• Original Assignee: Verilink Corporation (ExeLED Holdings, Inc.)
• Inventors: Taylor, Steven C., Schas, Marc L.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): BERGMANN, SAUL
• Application Number:
  US06/648,124
• Time in Patent Office: 606 Days
• Field of Search: 340/347 DD, 370/100, 370/95, 370/99
• US Class Current: 341/87
• CPC Class Codes: H04J 3/1682 Allocation of channels according to the instantaneous demands of the users, e.g. concentrated multiplexers, statistical multiplexers
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

An interface apparatus utilizing data encoding/decoding methods having particular application for use in interfacing data processing and telecommunication equipment is disclosed. The interface apparatus includes an encoder for encoding inputted data for transmission on a telecommunication system, and a decoder to receive the encoded data and decode the data stream such that it identically represents data originally provided to the encoder. The present invention detects channels in the inputted data which contain a predetermined value of bits, and stores the channel numbers of these detected channels in digital storage means. These detected channels are then deleted from the data stream, and the remaining inputted data in each of the data channels is shifted such that data previously located in the first data channel is inserted in the data channel offset by the number of channels stored in the storage means. The present invention then inserts the channel numbers previously stored in the storage means in empty data channels created by the shifting process. This encoded data stream is then transmitted, and is received by another unit of the present invention coupled to receiving data processing equipment. A decoder of the present invention detects the channel numbers previously inserted into the data channels and stores these numbers in a channel address buffer. The decoder deletes the channel numbers in the data channels and shifts the data in the remaining channels, such that the received data is sequentially inserted beginning in the first data channel. Previously defined predetermined values are inserted in the now empty data channels which are identified by the channel numbers stored in the channel address buffer.

Claims

1. A method for encoding data for transmission from a first data processing unit to a second data processing unit, said data being organized into a plurality of sequential channels identified by channel numbers (1 . . . N), each of said data channels comprising a plurality (X) of bits, comprising the steps of:

(a) detecting channels in said data which contain a predetermined value of bits and storing the channel numbers of said channels in a first storage means;

(b) deleting data contents of said data channels which contain said predetermined value of bits from said data;

(c) shifting said remaining data in each of said data channels such that data previously stored in said first data channel is stored in a data channel offset by the number of channels stored in said first storage means;

(d) inserting the channel numbers previously stored in said first storage means in empty data channels created by said shifting step;

whereby said data is encoded for transmission to said second data processing device.

2. The method as defined by claim 1, wherein data is received and decoded by said second data processing unit using a method comprising the steps of:

detecting channel numbers previously inserted by said first data processing unit in data channels created by said shifting step, and storing said channel numbers in a channel address buffer;

deleting said channel numbers in said data channels, and shifting said data in said remaining channels such that received data is sequentially stored beginning in said first data channel;

shifting data located in data channels identified by said channel numbers stored in said channel address buffer, such that an empty channel is created for those channels identified by said stored channel numbers;

inserting said predetermined bit values in said now empty channels identified by said channel numbers stored in said channel address buffer;

whereby said data is decoded and corresponds to the original data provided to said first data processing unit.

3. The method as defined by claim 1, wherein said data is organized into a plurality of sequential frames comprising a plurality of data channels, each of said frames being delineated by a frame bit.

4. The method as defined by claim 3, wherein the logical states of said frame bits comprise a predetermined bit state sequence.

5. The encoding method as defined by claim 4, further including the step of altering said predetermined bit sequence of said frame bits.

6. The encoding method as defined by claim 5, wherein said predetermined frame bit sequence comprises the following logical states for each sequential frame bit:

space="preserve" listing-type="equation">1 0 0 0 1 1 0 1 1 1 0 0

7. The encoding method as defined by claim 6, wherein said altering step comprises altering the states of frame bits 4, 8 and 12.

8. The encoding method as defined by claim 5, wherein step (D) of said method further includes inserting a channel flag along with said channel number in said empty data channels, the logical state of said channel flag denoting whether subsequent data channels contain channel numbers.

9. The encoding method as defined by claim 8, wherein said predetermined bit values comprise logical zeros.

10. An interface apparatus including an encoder for encoding data for transmission from a first data processing unit to a second data processing unit, said data being organized into a plurality of sequential channels identified by channel numbers (1 . . . N), each of said data channels comprising a plurality (X) of bits, said encoder comprising:

input means for inputting and storing said data channels.

first detection means coupled to said input means for detecting channels in said data which contain a predetermined value of bits and storing the channel numbers of said channels in a first storage means;

deleting means for deleting data contents of said channels which contain said predetermined value of bits from said data;

first shifting means coupled to said deleting means for shifting said remaining data in each of said data channels, such that data previously stored in said first data channel is inserted in a data channel offset by the number of channels stored in said first storage means;

said shifting means further inserting the channel numbers previously stored in said first storage means in the empty data channels created;

whereby said data is encoded for transmission to said second data processing device.

11. The encoder as defined by claim 10, wherein said first storage means includes a random access memory (RAM) for storing said data and said channel address numbers.

12. The encoder as defined by claim 11, wherein said data to be encoded is inputted into a shift register, and said detection means includes a data flip-flop to detect channels having said predetermined value of bits.

13. The encoder as defined by claim 12, wherein said RAM is divided into input and output buffer sections for storing said data and channel addresses.

14. The encoder as defined by claim 13, further including an input channel data counter and an input channel address counter coupled to said RAM to control which buffer section said data and channel addresses are stored in said RAM.

15. The encoder as defined by claim 14, further including an output shift register coupled to said RAM and to a multiplexer for shifting said encoded data in a serial format to said second data processing system.

16. The encoder as defined by claim 15, wherein said multiplexer inserts altered frame bits between sequential frames of said encoded data, said frames comprising a plurality of data channels.

17. The interface apparatus as defined by claim 10, further including a decoder coupled to said second data processing unit, comprising:

receiving means for receiving and storing said encoded data from said first processing unit;

second detection means coupled to said receiving means for detecting channel numbers previously inserted by said first data processing unit in data channels created by said shifting means of said encoder, and storing said channel numbers in a channel address buffer, and deleting data contents of said channel numbers in said data channels and shifting said data in said remaining channels such that received data is sequentially stored beginning in said first data channel;

second shifting means coupled to said detection means for shifting data located in data channels identified by said channel numbers stored in said channel address buffer, such that an empty channel is created for those channels identified by said stored channel numbers;

insertion means coupled to said shifting means for inserting said predetermined bit values in said now empty channels identified by said channel numbers stored in said channel address buffer;

whereby said data is decoded and corresponds to the original data provided to said first data processing unit.

18. The interface apparatus as defined by claim 17, wherein said encoder includes a random access memory (RAM) for storing said data and said channel address numbers.

19. The interface apparatus as defined by claim 18, wherein said RAM is divided into input and output buffer sections for storing said data and channel addresses.

20. The interface apparatus as defined by claim 19, wherein said decoder includes an output shift register coupled to said RAM and to a multiplexer for shifting said decoded data in a serial format to said second data processing system.

21. The interface apparatus as defined by claim 20, wherein said multiplexer inserts frame bits between sequential frames of said decoded data, said frames comprising a plurality of data channels.

22. The interface apparatus as defined by claim 21, wherein said decoder includes a channel address counter and an output channel data counter coupled to said RAM to control which section of said RAM is read.

23. The interface apparatus as defined by claim 22, wherein said decoder includes a comparator to determine if the current channel number to be outputted to said second data processing unit is the same as the current channel address in said output buffer.