Method for making vertical channel field controlled device employing a recessed gate structure

• US 4,587,712 A
• Filed: 01/17/1985
• Issued: 05/13/1986
• Est. Priority Date: 11/23/1981
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Baliga, Bantval J.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Schiavelli, Alan E.
• Application Number:
  US06/692,073
• Time in Patent Office: 481 Days
• Field of Search: 29/571, 29/576 E, 29/580, 29/591, 148/DIG. 50, 148/175, 148/DIG. 88, 357/22, 357/381, 357/55
• US Class Current: 438/137
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/66416 Static induction transistors [SIT] with an active layer made of a group 13/15 material H01L29/66454

Abstract

A vertical channel junction gate electric field controlled device (e.g., a field effect transistor, or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves, generally on the upper surface of the base region layer, are upper electrode regions, for example, source electrode regions or cathode electrode regions. Recessed in the grooves are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions in the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection. The structure facilitates fabrication by methods, also disclosed, which avoid any critical photolithographic alignment steps in masking to define the location of the source (or cathode) and gate regions, and avoid the need for any mask or mask alignment for metal definition when forming electrode metallization.

Claims

1. A method of fabricating a vertical channel junction gate electric field device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising:

providing a semiconductor wafer having a base layer of the one conductivity type;

forming an electrode layer of one conductivity type atop the base layer;

forming grooves through said electrode layer and extending into the base layer, such that said grooves divide said upper electrode layer into upper electrode regions between said grooves;

partially refilling said grooves to thereby form junction gate regions of opposite conductivity type recessed in said grooves; and

depositing metal onto the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode region, and metallized recessed gate terminals in ohmic contact with the junction gate regions recessed in the grooves.

2. A method in accordance with claim 1, wherein the grooves are formed with elongated shape, and wherein the gate regions, upper electrode regions, and metallized terminals are all formed with elongated shape.

3. A method in accordance with claim 2, wherein the grooves are formed with substantially vertical sidewalls.

4. A method in accordance with claim 1, which further comprises:

forming a recessed gate contact pad area adjacent to and at generally the same level as the bottoms of the grooves; and

depositing metal onto the gate contact pad area to form a gate contact pad as a physical and electrical extension of the gate terminal metallization.

5. A method in accordance with claim 1, which further comprises, prior to the step of depositing metal onto the wafer surface, forming an oxide layer with a slight overhang over the edges of the grooves so as to minimize the deposition of metal on the groove sidewalls.

6. A method in accordance with claim 2, which further comprises, prior to the step of depositing metal onto the wafer surface, forming an oxide layer with a slight overhang over the edges of the grooves so as to minimize the deposition of metal on the groove sidewalls.

7. A method of fabricating a vertical channel junction gate electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising:

providing a semiconductor wafer having a base layer of the one conductivity type and of crystallographic orientation selected to facilitate preferential etching and the formation of substantially vertical-walled gate grooves;

forming at the upper surface of the base layer an upper electrode region layer of the one conductivity type but of higher conductivity than the base layer;

forming a layer of silicon dioxide with a plurality of elongated windows on the upper surface of the upper electrode region, the windows defining the ultimate locations of the gate regions and the oxide layer portions between the windows defining the ultimate locations of upper electrode regions;

preferentially etching the upper electrode region layer and the base layer to form substantially vertically-walled gate grooves below the windows;

partially refilling the grooves with semiconductor material of the opposite conductivity type to provide a gate structure;

removing the silicon dioxide layer to expose the upper electrode regions; and

evaporating metal onto the the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode regions and elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

8. A method in accordance with claim 7, which comprises the further step of lightly etching the grooves to remove any metal evaporated onto the groove sidewalls.

9. A method in accordance with claim 7, wherein the upper electrode region is formed by diffusion.

10. A method in accordance with claim 7, wherein the step of partially refilling the grooves with semiconductor material of the opposite conductivity type to form a gate structure comprises:

refilling the grooves with semiconductor material of the opposite conductivity type by epitaxial growth; and

preferentially etching the refilled grooves to remove a predetermined fraction of the semiconductor material of the opposite conductivity type to define the thickness of the gate structure.

11. A method in accordance with claim 7, wherein the step of partially refilling of the grooves with semiconductor material of the opposite conductivity type to form a gate structure comprises partially refilling the grooves with semiconductor material of the opposite conductivity type by epitaxial growth.

12. A method in accordance with claim 7, which further comprises:

etching the base layer to form a recessed gate contact pad area at the same level as the bottoms of the grooves; and

evaporating metal onto the gate contact pad area to form a gate contact pad as a physical and electrical extension of the gate terminal fingers.

13. A method in accordance with claim 7, wherein the base layer provided is of N- conductivity type, the diffused source regions formed are of N+ conductivity type, and the diffused junction gate regions formed are of P+ conductivity type.

14. A method in accordance with claim 7, wherein the base layer comprises silicon with a <

110>

surface crystallographic orientation and with a set of <

111>

planes at right angles to the <

110>

surface, and the elongated windows are defined along the <

211>

direction.

15. A method of fabricating a vertical channel junction gate electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising:

providing a semiconductor wafer having a base layer of the one conductivity type and of crystallographic orientation selected to facilitate preferential etching and the formation of substantially vertically walled gate grooves;

forming at the upper surface of the base layer an upper electrode region layer of the one conductivity type but of higher conductivity than the base layer;

forming a layer of silicon dioxide with a plurality of parallel elongated windows on the upper surface of the upper electrode region, alternate windows defining the ultimate locations of upper electrode region contacts and gate regions;

forming an etchant barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of upper electrode region contacts and to leave open the windows in the silicon dioxide layer defining the ultimate location of gate regions;

preferentially etching the upper electrode region layer and the base layer to form substantially vertically-walled grooves beneath the gate region windows, with undercutting of the oxide layer surrounding the gate region windows;

partially refilling the grooves with semiconductor material of the opposite conductivity type to provide a gate structure;

removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of the upper electrode region contacts; and

evaporating metal onto the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

16. A method in accordance with claim 15, wherein the step of partially refilling of the grooves with semiconductor material of the opposite conductivity type to form a gate structure comprises:

refilling the grooves with semiconductor material of the opposite conductivity type by epitaxial growth; and

preferentially etching the refilled grooves to remove a predetermined fraction of the semiconductor material of the opposite conductivity type to define the thickness of the gate structure.

17. A method in accordance with claim 15, wherein the step of partially refilling the grooves with semiconductor material of the opposite conductivity type to form a gate structure comprises partially refilling the grooves with semiconductor material of the opposite conductivity type by epitaxial growth.

18. A method in accordance with claim 15, wherein the upper electrode region is formed by diffusion.

19. A method in accordance with claim 15, which further comprises:

etching the base layer to form a recessed gate contact pad area at the same level as the bottoms of the grooves; and

evaporating metal onto the gate contact pad area to form a gate contact pad as a physical and electrical extension of the gate terminal fingers.

20. A method in accordance with claim 15, wherein the base layer provided is of N- conductivity type, the diffused source regions formed are of N+ conductivity type, and the diffused junction gate regions formed are of P+ conductivity type.

21. A method in accordance with claim 15, wherein the base layer which is provided is silicon with a <

110>

surface crystallographic orientation, with a set of <

111>

planes at right angles to the <

110>

surface, and the parallel elongated windows are defined along the <

211>

direction.