Method of fabrication of long arrays using a short substrate

• US 4,587,719 A
• Filed: 06/05/1984
• Issued: 05/13/1986
• Est. Priority Date: 08/01/1983
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Inventors: Barth, Phillip W.
• Primary Examiner(s): Walton, Donald L.
• Assistant Examiner(s): HEARN, BRIAN E
• Application Number:
  US06/617,304
• Time in Patent Office: 707 Days
• Field of Search: 29/572, 29/573, 29/577 R, 29/577 C, 29/580, 29/581, 29/582, 29/583, 29/588, 29/591, 148/DIG. 28, 357/49, 357/69, 357/72, 361/398, 374/178
• US Class Current: 438/113
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0393 Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups

Abstract

A method of forming a flexible array of circuit elements and electrical contacts where parallel lines of conductors joined by short perpendicular line of conductors are folded both about an axis parallel to the perpendicular line of elements and about an axis parallel to parallel lines thereby forming a linear array.

Claims

1. A method of forming a flexible array of circuit elements and electrical contacts interconnected by continuous wires, comprising the steps of

(a) providing a body of semiconductor material having opposed major surfaces,

(b) forming a plurality of said circuit elements on first major surface of said body,

(c) providing conductive interconnections on said first major surface to interconnect said circuit elements, said conductive interconnections forming two or more substantially parallel, substantially linear regions, such regions connected at their ends by shorter regions substantially perpendicular to said parallel regions in such a manner as to form a continuous meandering path,

(d) attaching a flexible polymer layer to said conductive interconnections and said first major surface,

(e) providing an opening or openings in said polymer layer to allow contact to said conductive interconnections,

(f) removing portions of said body of semiconductor material by etching, leaving separated islands of semiconductor material supported by said polymer layer,

(g) attaching an additional polymer layer over the second major surface of said islands and polymer, forming a resulting layer of polymer which encases said islands

(h) cutting said resulting polymer layer between and substantially parallel to said parallel regions, but not through said perpendicular regions,

(i) folding the said resulting polymer layer through an angle of approximately 180°

about an axis perpendicular to said parallel regions, where such fold point is at or near the juncture of said perpendicular region with one of said parallel regions, and then

(j) folding the said resulting polymer layer through an angle of approximately 180°

about an axis parallel to said parallel regions, where such fold point is at or near the juncture of said perpendicular region with the other adjacent parallel region, and

(k) fastening said resulting shape to make it retain its folded shape.

2. A method as claimed in claim 1 wherein said array forms a substantially linear shape after fabrication.

3. A method as claimed in claim 1 wherein said array is an array of silicon diodes connected by metal wires.

4. A method as claimed in claim 1 where steps (i) and (j) are reversed in order.

5. A method as claimed in claim 1 wherein more than two folds are used to provide substantially the same resulting shape wherein the adjacent, formerly parallel regions become substantially co-linear.

6. The method of claim 1 including the further step of preventing tearing at or near folded regions of said resulting polymer layer by forming a substantially circular hole in said resulting polymer layer before said resulting polymer layer is folded, which hole intersects the end of a linear cut also formed in said resulting polymer layer before the folding operation.

7. The method of claim 1 including the further step of preventing kinks and breaks in folded regions of said resulting polymer layer by inserting a wire or other body used as a mandril into the interior angle of the fold during the folding process, with the effect that the radius of the fold is, at a minimum, equal to the radius of the mandril.

8. A method as claimed in claim 7 wherein said mandril is removed after the folding process.

9. A method as claimed in claim 7 wherein said mandril remains as part of the finished array structure.

10. A method as claimed in claim 1 wherein adhesion promoters are applied to surfaces before the application of said flexible polymer to that surface.

11. A method as claimed in claim 10 wherein said adhesion promoter is an aluminum chelate, used in conjunction with polyimide as the said flexible polymer.

12. A method as in claim 7 where steps (i) and (j) are reversed in order.

13. A method as in claim 7 wherein more than two folds are used to provide substantially the same resulting shape wherein the adjacent, formerly parallel regions become substantially co-linear.

14. A method as in claim 12 wherein said array forms a substantially linear shape after fabrication.

15. A method as in claim 13 wherein said array is an array of silicon diodes connected by metal wires.