Local area network interface controller

• US 4,590,467 A
• Filed: 10/13/1983
• Issued: 05/20/1986
• Est. Priority Date: 10/13/1983
• Status: Expired due to Term

• Current Assignee: PCTEL, Inc. (Amphenol Corporation)
• Original Assignee: Rockwell International Corporation
• Inventors: Lare, Lawrence E.
• Primary Examiner(s): YUSKO, DONALD
• Application Number:
  US06/541,817
• Time in Patent Office: 950 Days
• Field of Search: 340/825.5, 340/825.05, 370/85, 370/86, 178/71 R
• US Class Current: 370/462
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]

Abstract

A network controller includes an interface unit connected to a communication network channel for transferring data in the form of information packets to and from the channel; a receive buffer connected for storing in parallel form the data packets transferred from the communication channel; and first and second shift registers having n bit positions including a pointer bits to the receive buffer, circulating at different clock rates corresponding to the clock rate of data on said communication channel and the clock rate of the system bus.

Claims

1. In data communications network having a plurality of information processing systems coupled to a communication channel which serially transmits data in the form of information packets at a first clock rate, a network controller disposed between said communication channel and an information processing system including a system data bus having associated therewith a second clock rate, comprising:

an interface unit connected to said communication channel for transferring data in the form of information packets to and from said channel;

a de-serializer connected to said interface unit for converting data in said information packet received from said channel from serial form to parallel form;

a receiver buffer connected to said de-serializer for storing in parallel form the data corresponding to a plurality of information packets transferred from said communication channel;

a first shift register having n bit positions including a first pointer bit, and circulating at a first clock rate corresponding to the clock rate of data on said communication channel, where n corresponds to the number of memory locations in said receive buffer, the location of said pointer bit with respect to said n bit positions in said first shift register corresponding to and pointing to the memory location in said receiver buffer wherein said data from said de-serializer is to transmit the data into said receive buffer; and

a second shift register having n positions, including a second pointer bit, and circulating at said second clock rate corresponding to the clock rate of said system bus, the location of said second pointer bit with respect to said n bit positions corresponding to and pointing to the memory location in said receive buffer wherein data stored in said receive buffer is to be transferred to said system bus during the next memory cycle of said system bus.

2. A controller as defined in claim 1, further comprising an edge detector connected to said first shift register to detect a signal transition indicative that a predetermined number of bit positions with respect to said n bit positions have been cycled through by said first pointer bit, to generate an enabling signal therefrom.

3. A data communication system comprising:

a communication medium;

a plurality of transceivers coupled to said medium, each transceiver including transmitting means for transmitting a signal onto said medium, and receiving means for receiving a signal communicated on said medium by another transceiver;

collision detecting means coupled to the transmitting means and the receiving means of each transceiver for generating a collision signal whenever a signal communicated on said medium by another transceiver is received by said receiving means during the time said transmitting means is transmitting a signal onto said communicating medium;

means connected to each transceiver and responsive to the presence of said collision signal for interrupting the transmission of a signal onto said medium by said transmitting means;

means connected to each transceiver and responsive to the presence of a carrier signal on said channel for preventing the transmission of a signal by said transmitting means;

an interface unit connected to said transceiver for transferring data in the form of information packets to and from said communication medium;

a de-serializer connected to said interface unit for converting data in said information packet received from said transceiver from serial form to parallel form;

a receive buffer having n memory locations, where n is an integer, connected to said de-serializer for storing in parallel form the data in said information packets transferred from said communication channel;

a first shift register having n bit positions, and circulating at a first clock rate corresponding to the data rate of data transmitted in said communication medium where n corresponds to the number of memory locations in said receive buffer, the location of a pointer bit with respect to said n bit positions in said first shift register corresponding to and pointing to the m th memory location in said receive buffer wherein said data from said serializer is to transmit the data into said receive buffer during the next memory cycle; and

a second shift register having n bit positions and circulating at a second clock rate corresponding to the clock rate of said system bus, said second shift register including a pointer bit having a location with respect to said n bit positions corresponding to and pointing to the m th memory location in said receive buffer wherein data in said receive buffer memory is to be transferred to said system bus during the next memory cycle of said system bus.