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Local area network interface controller

  • US 4,590,467 A
  • Filed: 10/13/1983
  • Issued: 05/20/1986
  • Est. Priority Date: 10/13/1983
  • Status: Expired due to Term
First Claim
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1. In data communications network having a plurality of information processing systems coupled to a communication channel which serially transmits data in the form of information packets at a first clock rate, a network controller disposed between said communication channel and an information processing system including a system data bus having associated therewith a second clock rate, comprising:

  • an interface unit connected to said communication channel for transferring data in the form of information packets to and from said channel;

    a de-serializer connected to said interface unit for converting data in said information packet received from said channel from serial form to parallel form;

    a receiver buffer connected to said de-serializer for storing in parallel form the data corresponding to a plurality of information packets transferred from said communication channel;

    a first shift register having n bit positions including a first pointer bit, and circulating at a first clock rate corresponding to the clock rate of data on said communication channel, where n corresponds to the number of memory locations in said receive buffer, the location of said pointer bit with respect to said n bit positions in said first shift register corresponding to and pointing to the memory location in said receiver buffer wherein said data from said de-serializer is to transmit the data into said receive buffer; and

    a second shift register having n positions, including a second pointer bit, and circulating at said second clock rate corresponding to the clock rate of said system bus, the location of said second pointer bit with respect to said n bit positions corresponding to and pointing to the memory location in said receive buffer wherein data stored in said receive buffer is to be transferred to said system bus during the next memory cycle of said system bus.

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