Token access controller protocol and architecture

• US 4,590,468 A
• Filed: 03/10/1983
• Issued: 05/20/1986
• Est. Priority Date: 03/10/1983
• Status: Expired due to Fees

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Western Digital Corporation
• Inventors: Stieglitz, Mark
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US06/474,135
• Time in Patent Office: 1,167 Days
• Field of Search: 340/825.5, 340/825.52, 455/607, 370/85, 370/90, 370/94, 370/96, 364/200, 364/900
• US Class Current: 370/450
• CPC Class Codes: H04L 12/417 with deterministic access, e.g. token passing

Abstract

Disclosed is a token access protocol for a local area network and the architecture for a token access controller to implement this protocol. The protocol provides for network initialization, recovery and addition of nodes to the network. The host of each node has a minimal involvement with maintaining the network and the protocol does not require the host processor to format frames for transmission. Data reception or transmission is facilitated through the use of a Direct Memory Access (DMA) so the host processor is freed to perform other tasks while data is being transmitted or received.

Claims

1. A token access controller for controlling the transmission of information fields over a network comprising a plurality of nodes connected by a transmission medium for transmitting frames, wherein each node has been assigned an unique network address and each node has a token access controller, host processor, memory, and internal bus and interface means to connect said internal bus to said transmission medium, said token access controller comprising:

means for passing the right to transmit any information field between nodes, wherein the node that has the right to transmit any information field is the only node that is enabled to transmit on the transmission medium of the network and all other nodes can only be enabled to receive the transmitted frames;

means for determining when said token access controller has finished transmitting;

means for determining the successor node, wherein the successor node is the node that said token access controller shall pass the token to when said node finishes transmitting and the successor node is unique;

means for the host processor of the node of said token access controller to instruct said token access controller where information to be transmitted is stored in the memory of the node of said token access controller;

means for transmitting information stored in the memory of the node of said token access controller to another node without the aid of the host processor of the node of said token access controller once said host processor instructs said token access controller of the location of the information in its memory;

means for the host processor of the node of said token access controller to instruct said token access controller where information to be received from another node should be stored in the memory of the node of said token access controller; and

means for receiving information from another node and storing the information in the memory of the node of said token access controller without the aid of the host processor of the node of said token access controller once said host processor instructs the token access controller where the information should be stored.

2. A token access controller as described in claim 1, wherein the token access controller is part of said interface means.

3. A token access controller as described in claim 2 further including:

means for network initialization;

means for sending an acknowledgement information field upon receiving an information field wherein said token access controller indicates whether a transmission was received;

means for reestablishing the network if the token is lost; and

means for eliminating duplicate tokens.

4. A token access controller as described in claim 2, wherein all information fields are frames transmitted on the transmission medium that start with a flag comprising a unique predefined field and end with a Frame Check Sequence and said flag, said token access controller further including:

a receiver comprising means for detecting the flag at the start of the information field, means for verifying whether the Frame Check Sequence is correct, means for informing the token access controller of the result of the Frame Check Sequence, and means for detecting the flag at the end of a frame; and

a transmitter comprising means for creating the flag at the start of the information field, means for generating the Frame Check Sequence and means for detecting the flag at the end of the frame.

5. A token access controller as described in claim 2, further including:

means for central polling of nodes desiring to enter the network, wherein one node transmits a predefined information field over the entire range of addresses of nodes to determine if any nodes want to enter the network;

means for distributed polling of nodes desiring to enter the network, wherein each node transmits a predefined information field over a limited range of addresses to determine if any nodes want to enter the network;

means for the host processor to change the successor node to a different node.

6. A token access controller for controlling the transmission of information over a network comprising a plurality of nodes connected by a transmission medium, with only one node having the right to transmit information on the transmission medium at any given time, wherein each node is assigned a unique network address and a unique next node address corresponding to a node that will have the subsequent right to transmit information and wherein each node has a token access controller, host processor, memory, internal bus and interface means coupled to the transmission medium, said token access controller comprising:

right to transmit detecting means for detecting on the network the transmission of the network address of the node of said token access controller;

first circuit means responsive to the right to transmit detecting means for determining whether the token access controller is to transmit information onto the network;

right to transmit passing means responsive to the first circuit means for transmitting onto the network information including the next node address; and

second circuit means responsive to the right to transmit passing means for enabling the receiving of information transmitted on the network after the transmission of the next node address.

7. A token access controller chip as described in claim 6, wherein the second circuit means further includes alterable register memory means for governing the actions of the right to transmit detecting means, first circuit means, right to transmit passing means and second circuit means, wherein the host processor and the controller may alter the contents of at least some of the registers and the second circuit means may alter the contents of some of the registers in response to information transmitted on the network.

8. A token access controller as described in claim 7, wherein all information is transmitted in a frame format on the transmission medium and some frames include at least one destination information field representing the network address of which node or nodes is to receive the information, wherein the second circuit means further includes:

a "my address" memory means for storing the network address of the node;

comparator means for comparing the value in the destination field with the network address stored in the "my address" memory means; and

direct memory access means responsive to the comparator means for storing at least part of the information received from the network in the memory of the node.

9. A token access controller as described in claim 8, wherein the destination information field may be a global broadcast address and wherein the comparator means further includes first means for determining if the destination information field is the global broadcast address and the direct memory access means includes second means responsive to the first means for storing at least part of the information received from the network in the memory of the node.

10. A token access controller as described in claim 6, wherein the token access controller further includes a clock input adapted to receive to a clock signal, wherein the token access controller further includes:

a host processor alterable network dead memory means for storing a value provided by the host processor;

receiving means coupled to the interface means for detecting the transmission of information on the network;

network dead timer means responsive to the receiving means and coupled to the clock input for counting the number of clock pulses in the clock signal since the receiving means detected the transmission of information;

comparator means for determining if the counted number of clock pulses exceeds the value stored in the network dead memory means; and

reestablishment means responsive to the comparator means for determining if there is another node connected to the network.

11. A token access controller as described in claim 10, wherein the token access controller includes:

resetting means responsive to the receiver means for resetting the counted number of clock pulses in the network dead timer means to zero whenever the receiver means detects information being transmitted on the network.

12. A token access controller as described in claim 11, wherein there is a maximum number of nodes that may be connected to the network and wherein the token access controller further includes permanent memory means for storing a program for controlling the circuit means, and the reestablishment means includes:

an acknowledgement timer means coupled to the interface means and responsive to the passing of the token for monitoring the transmission medium for a specified period of time after passing the token and providing a first logic signal if a transmission is detected and a second logic signal if no transmission is detected within the specified period of time;

a "scratch pad" memory means for storing a value supplied by the circuit means;

a "my address" memory means for storing the value of the network address of the node;

a "next address" memory means for storing the value of the next node network address of the node; and

a controller means for;

(a) storing the value in the "next address" memory means in the "scratch pad" memory means;

(b) determining if the value stored in the "scratch pad" memory means is greater than the maximum number of nodes that may be connected to the network and storing a one in the "scratch pad" memory means if the contents in the "scratch pad" memory means exceeds the maximum value;

(c) determining if the contents of the "scratch pad" memory means equals the contents of the "my address" memory means and if the contents are not equal, then causing the right to transmit passing means to transmit a network address equal to the contents of the "scratch pad" register;

(d) waiting for the acknowledgement timer means to provide the first signal and then setting the contents of the "next address" memory means equal to the contents of the "scratch pad" memory means; and

otherwise

(e) incrementing the contents of the "scratch pad" memory means and repeating steps a through e.

13. A token access controller as described in claim 6, wherein the node has a clock coupled to the token access controller and wherein the token access controller further includes:

first means for determining whether the token access controller should wait for an acknowledgement signal from another node before transmitting additional information;

receiver means coupled to the interface means for detecting the transmission of an acknowledgement signal on the network;

host processor alterable acknowledgement memory means for storing a value representing how long the node should wait for an acknowledgement from another node;

acknowledgement timer means responsive to the first means for counting clock pulses from the clock;

comparator means for determining when the counted number of clock pulses exceeds the value stored in the acknowledgement memory means; and

seccond means responsive to the comparator means and to the receiver means for alerting the host processor whether an acknowledgement was received from another node.

14. A token access controller as described in claim 6, wherein information transmitted on the network is transmitted according to a specific frame format with each frame beginning with a flag bit pattern and each frame ending with an error detecting code followed by a flag bit pattern and each frame having further information between the beginning and the end of the frame, with the number of bits of the further information varying with the type of information being transmitted, wherein the second circuit means further includes:

frame type means for detecting whether the number of bits of further information exceeds at least a first limit, whereby the token access controller recognizes the type of further information being transmitted.

15. A token access controller as described in claim 14, wherein information transmitted on the network is one of three types, with the number of bits of further information is a first number for a first type of information, is a second number for a second type of information and is a number greater than the first or second number for the third type of information, wherein the frame type means includes means for detecting if the number of bits equals the first number or the second number or exceeds the number of bits of the first and second number.

16. A token access controller as described in claim 15, wherein the first type of information calls for passing the token, the second type of information calls for transmitting certain information about the status of the token access controller and the third type of information calls for information being transmitted from one host processor to another host processor.

17. A token access controller as described in claim 15, wherein a particular pattern of a particular number of bits of further information calls for one or more nodes to enter a scanning mode for searching for additional nodes desiring to enter the network, wherein the token access controller includes:

"my address" memory means for storing the value of the network address of the node of the token access controller;

"next address" memory means for storing the value of the network address of the node to which the token access controller should pass the token;

scanning detecting means responsive to the frame type means for determining if the circuit means is to cause the token access controller to enter the scanning mode; and

incrementing means responsive to the scanning detecting means for adding a one to the value stored in the "my address" memory means and storing that sum in the "next address" memory means.

18. A token access controller as described in claim 14, wherein a frame of at least one length is used for reassigning the right to transmit information to another node with the node to which the token is being passed is specified by a specific bit pattern occuring at a specific point in the frame of at least one length and representing the network address of the node to which the token is being passed, the right to transmit detecting means comprises:

"my address" memory means for storing the value of the network address of the node of the token access controller;

token frame detecting means responsive to the frame type detecting means for determining if the frame is of the type used for passing the token;

token detecting means responsive to the token frame detecting means for comparing the specific bit pattern with the value stored in the "my address" memory means; and

transmitter means operative in response to the token detecting means for transmitting information stored in the host memory onto the network.

19. A token access controller as described in claim 14, wherein a frame of at least one length is used for transmitting further information, wherein the node to which the information is being transmitted is specified by a specific bit pattern occuring at a specific point in the frame and representing the network address of the node to which the information is being transmitted, the circuit means comprising:

"my address" memory means for storing the value of the network address of the node of the token access controller;

destination detecting means responsive to the frame type means for comparing the specific bit pattern with the value stored in the "my address" memory means; and

receiver means responsive to the destination detecting means for storing at least part of the further information in the memory of the host processor.

20. A token access controller as described in claim 6, wherein the right to transmit passing means includes:

a host processor alterable access holdoff memory means for storing the number of times the token access controller should hold off from transmitting before transmitting information onto the network after detection of the network address of the node of said token access controller;

a limit memory means for storing the number of tokens the token access controller has received since the token access controller last transmitted information;

a compararor means for comparing the value stored in the holdoff memory means with the value stored in the limit memory means; and

token passing means responsive to the comparator means for immediately causing the right to transmit passing means to transmit whenever the value stored in the holdoff memory means is greater than the value stored in the limit memory means.

21. A token access controller as described in claim 20, wherein the token access controller further includes:

host alterable "transmitter not enabled" means for preventing the token access controller from transmitting information onto the network and for immediately causing the right to transmit passing means to transmit the next address upon the detecting means detecting the network address of the node.

22. A token access controller as described in claim 6, wherein information is transmitted on the network in data frames and wherein the token access controller includes:

host alterable memory means for storing the maximum amount of data frames the token access controller can transmit onto the network each time the right to transmit detecting means detects the network address of the node;

"scratch pad" memory means for storing the number of data frames that the token access controller has transmitted since receiving the token;

incrementing means responsive to the transmission of a data frame onto the network by the token access controller for adding one to the value stored in the "scratch pad" memory means;

comparator means for comparing the value stored in the "scratch pad" memory means with the value stored in the host alterable memory means; and

transmission prevention means responsive to the comparator means for preventing the transmission of more data frames prior to the right to transmit means transmitting the network address whenever the comparator indicates that the value stored in the host alterable memory means equals the value stored in the "scratch pad" memory means.

23. A token access controller as described in claim 6, wherein the token access controller further includes:

a host alterable memory means for indicating if the token access controller is to ignore any information transmitted on the network including the transmission of the network address of the node of said token access controller; and

controller means operable in response to the memory means for preventing the circuit means from transmitting information and receiving information;

whereby the node is isolated from the network.

24. A token access controller as described in claim 15, wherein a particular bit pattern of a particular number of bits occuring at a specified point in the frame instructs the node receiving the transmitted information that the receiving node should acknowledge receipt of the transmitted information, wherein the token access controller comprises:

acknowledgement request detecting means responsive to the frame type detecting means for determining if the node that transmitted the information is requesting an acknowledgement message;

acknowledgement message generating means responsive to the acknowledgement request detecting means for determining whether the transmitted information was correctly received by the token access controller; and

means for transmitting the acknowledgement message.