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Apparatus for synchronizing and allocating processes among several processors of a data processing system

  • US 4,590,555 A
  • Filed: 12/11/1980
  • Issued: 05/20/1986
  • Est. Priority Date: 12/11/1979
  • Status: Expired due to Term
First Claim
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1. A data processing system comprising plural individual data processors, a main memory for storing processes to be executed by the data processors, a process control block being stored in the main memory for each process, the process control block including:

  • for each process (a) a priority level, (b) a status indicator, (c) a start address in the main memory, and (d) the value of a process instruction count indicative of an execution point in the process where the process was previously interrupted, the main memory including for each processor (a) a status indicator and (b) address field, the main memory including plural areas for storing the processes in waiting queues, the storing areas being arranged in priority levels. the storing areas in like priority levels being linked together. each storing area having data assembled in a format to indicate (a) an address of a following process link in the waiting queue, (b) the priority of the process, (c) the number of the process corresponding to the process link, and (d) a mask for each processor, means responsive to (1) the status indicators for the processors, (2) the address field, (3) masks for the processor and (4) the priority levels of processes in the main memory for calculating an allocation of the processes to the processors, means responsive to the calculated allocation for selectively interrupting a process being executed by a first processor, the first processor being the processor selected by the means for calculating, means responsive to the first processor being interrupted for transferring all signals for the process being executed by the first processor from the first processor to the main memory so that the main memory stores (1) interrupted process, (2) the interrupted process status indicator, and (3) the instruction count of the interrupted process in the first processor, and means for transferring signals for the interrupting process from the main memory to the first processor so that the first processor begins executing the interrupting process at the instruction of the interrupting process indicated by the value of the instruction count of the interrupting process when the interrupting process was previously interrupted.

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