Apparatus for synchronizing and allocating processes among several processors of a data processing system

• US 4,590,555 A
• Filed: 12/11/1980
• Issued: 05/20/1986
• Est. Priority Date: 12/11/1979
• Status: Expired due to Term

• Current Assignee: Compagnie Internationale Pour L'Informatique Cii-Honeywell Bull
• Original Assignee: Compagnie Internationale Pour L'Informatique Cii-Honeywell Bull
• Inventors: Bourrez, Jean-Marie
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/215,522
• Time in Patent Office: 1,986 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/131, 364/133
• US Class Current: 718/103
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

Applicant processes to be performed on several processors in a data processing system are synchronized and allocated. The data processing system includes plural processors, each of which derives a control signal indicating that an event has occurred which requires a change in the status of the system, as well as registers for storing signals indicative of a process being executed by the processor. A memory common to the processors is selectively coupled to the processors via a bus. A circuit connected to the memory, the bus and selectively coupled to the processors selectively couples signals between a selected processor and the memory via the bus. The applicant processes are allocated and synchronized by a first circuit responsive to the control signal that allocates one of the processors to an applicant process and by second circuit that couples signals for the process being executed by the allocated processor at the time the control signal is coupled to the allocated process from the registers of the allocated processor to the memory via the data bus which thereafter couples signals for the applicant process from the memory to the registers of the allocated processors via the bus.

Claims

1. A data processing system comprising plural individual data processors, a main memory for storing processes to be executed by the data processors, a process control block being stored in the main memory for each process, the process control block including:

for each process (a) a priority level, (b) a status indicator, (c) a start address in the main memory, and (d) the value of a process instruction count indicative of an execution point in the process where the process was previously interrupted, the main memory including for each processor (a) a status indicator and (b) address field, the main memory including plural areas for storing the processes in waiting queues, the storing areas being arranged in priority levels. the storing areas in like priority levels being linked together. each storing area having data assembled in a format to indicate (a) an address of a following process link in the waiting queue, (b) the priority of the process, (c) the number of the process corresponding to the process link, and (d) a mask for each processor, means responsive to (1) the status indicators for the processors, (2) the address field, (3) masks for the processor and (4) the priority levels of processes in the main memory for calculating an allocation of the processes to the processors, means responsive to the calculated allocation for selectively interrupting a process being executed by a first processor, the first processor being the processor selected by the means for calculating, means responsive to the first processor being interrupted for transferring all signals for the process being executed by the first processor from the first processor to the main memory so that the main memory stores (1) interrupted process, (2) the interrupted process status indicator, and (3) the instruction count of the interrupted process in the first processor, and means for transferring signals for the interrupting process from the main memory to the first processor so that the first processor begins executing the interrupting process at the instruction of the interrupting process indicated by the value of the instruction count of the interrupting process when the interrupting process was previously interrupted.

2. A data processing system for executing several processes comprising several individual processors susceptible of having different states, a memory, means including transmission channel for selectively connecting each processor to the memory, the memory storing an execution allocation of the processes to the processors, the allocation of the processes to the processor being susceptible to changes in state, means coupled to the memory for controlling the allocation of the plural processes susceptible for execution by said processors, means included in each processor and coupled via the channels to the means for controlling the allocation and to the other processors for selecting particular processors of the system to perform said allocation of the plural processes susceptible for execution by said processors, said selecting means of each processor including:

first signal deriving means, said first signal deriving means being coupled via the channels to the means for controlling the allocation and responding to a change in allocation state of the processes of the system awaiting execution and for storing an indication of the change of allocation state, said first signal deriving means also being coupled to the processors via the channels and being responsive to a change in operating state of the processors to authorize the processor which changed operating state to execute the allocation of the plural processes susceptible for execution by several processors to the processors of the system, a second signal deriving means coupled via the channels to be responsive to the system processors for storing an indication that said allocation is already being performed by any processor, the first signal deriving means being connected to be responsive to the indication stored by the second signal deriving means for preventing execution of the allocation of the plural processes susceptible for execution by said processors to the processors of the system.

3. The system of claim 2 wherein the second signal deriving means comprises a counter having a count to indicate the number of allocation operations of the processes to the processors which have not been completed.

4. The system of claim 3 wherein the second signal deriving means comprises a bistable locking means for locking the system when a processor is selected.

5. The system of claim 4 wherein said main memory includes zones containing queueing lines of the plural processes susceptible to execution by the several processors, said locking means includes means for blocking access to the zones of the main memory containing the queueing lines in response to a modification in the allocation state of the processes, the access being blocked in such a manner that access to said zone is reserved only for the processor performing a distribution of the processes between all of the system processors.

6. The system of claim 5 wherein the first signal deriving means also comprises means for indicating process interlinkages of the queueing lines each time a process is allocated to a processor of the system.

7. The system of claim 6 wherein each processor includes registers to which each process susceptible to implementation is assigned, further comprising means coupled to the processors for emptying the state of the registers of each processor to which a process susceptible to implementation is assigned has been allocated in response to the processor to which the candidate process has been allocated implementing another process, means for loading the registers of the processors, said means for emptying being coupled with the means for loading the registers of the selected processor with parameters required for implementation of the process which is allocated to it.

8. The system of claim 2 wherein the second signal deriving means comprises a bistable locking means for locking the system when a processor is selected.

9. The system of claim 8 wherein said main memory includes zones containing queueing lines of the plural processes susceptible to execution by the several processors, said locking means includes means for blocking access to the zones of the main memory containing the queueing lines in response to a modification in the allocation state of the processes, the access being blocked in such a manner that access to said zones is reserved only for the processor performing a distribution of the processes between all of the system processors.

10. The system of claim 2 wherein the main memory stores queueing lines of the processes susceptible to execution by the system, the queueing lines for the processes being interlinked with each other on a priority basis, the first signal deriving means also comprising means for signalling an order in which the processes of the queueing lines are interlinked each time a process is allocated to a processor of the system.

11. The system of claim 2 wherein each processor includes registers to which each process susceptible to implementation is assigned, further comprising means coupled to the processors for emptying the state of the registers of each processor to which a process susceptible to implementation is assigned has been allocated in response to the processor to which the candidate process has been allocated implementing another process, means for loading the registers of the processors, said means for emptying being coupled with the means for loading the registers of the selected processor with parameters required for implementation of the process which is allocated to it.