Data processing system having dual processors

• US 4,591,975 A
• Filed: 07/18/1983
• Issued: 05/27/1986
• Est. Priority Date: 07/18/1983
• Status: Expired due to Term

• Current Assignee: Data General Corp. (Dell Technologies Inc.)
• Original Assignee: Data General Corp. (Dell Technologies Inc.)
• Inventors: Krantz, Lawrence L., Wagner, Eric M., Goodman, R. W., Wade, Donald A.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/515,089
• Time in Patent Office: 1,044 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/260
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A data processing system having a host processor and an attached processor is disclosed. Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing system memory but the host processor controls and performs all input and output operations for both processors. System memory is shared by the processors, therefore, only one processor is active on the bus system at any given time. Apparatus is disclosed for holding the host processor and starting the attached processor upon a command from the host and apparatus is disclosed for holding the attached processor and starting the host in the event of interrupt conditions, attempted access by the attached processor to protected areas of memory, or execution of an "out" instruction by the attached processor. Memory mapping apparatus which is under host control, but provides mapping for both the host and attached processors is shown.

Claims

1. In a data processing system having a first processor, a second processor, a memory, and bus means interconnecting the first processor, the second processor and the memory, a method for controlling which of said processors is active on said bus means, said method comprising the steps of:

(a) if said first processor is currently active, monitoring for a start command from said first processor to said second processor;

(b) if said start command to said second processor is detected, holding said first processor and starting said second processor;

(c) if said second processor is currently active, monitoring for an interrupt condition and monitoring for an attempt by said second processor to perform an input/output operation;

(d) if an interrupt condition is detected while said second processor is active, holding said second processor, starting said first processor and handling said interrupt condition;

(e) if an attempt by said second processor to perform an input or output operation is detected, holding said second processor, starting said first processor and performing the input or output operation;

(f) repeating steps (a)-(e).

2. The method of claim 1 further comprising the steps of

(a) said first processor identifying certain locations in said memory which are protected from access by said second processor;

(b) if said second processor is active, monitoring for an attempt by said second processor to access a portion of said protected memory locations; and

(c) if an attempt by said second processor to access a portion of said protected memory locations is detected, holding said second processor and starting said first processor.

3. A data processing system comprising:

memory means;

first processor means, said first processor means having means for executing computer programs under a first operating system and means for controlling all input and output operations of said data processing system;

second processor means, said second processor means having means for executing computer programs under a second operating system;

input/output device interface means;

bus means, connected to said memory means, said input/output device interface means, said first processor and said second processor;

for transferring at least data and addresses and

control means, connected to said first processor and said second processor, and said bus means for controlling which of said processors is allowed access to said bus means, said control means including

means for detecting an input or output request by said second processor,

means for holding said second processor when said second processor requests an input or output operation, and

means for starting said first processor when said second processor requests an input or output operation.

4. The data processing system of claim 3, further comprising:

means controlled by said first processor for mapping the logical addresses of said first processor and said second processor into the physical address space of said memory means; and

means controlled by said first processor for identifying portions of said memory means as being protected from access by said second processor.

5. The data processing system of claim 4, wherein said control means further comprises

means for detecting an attempt by said second processor to access a protected area of memory;

means, responsive to said memory access attempt detecting means, for holding said second processor and

means, responsive to said memory access attempt detecting means, for starting said first processor.

6. The apparatus of claim 3 wherein said bus control means further comprises:

means responsive to a command from said first processor for resetting said second processor;

means responsive to a command from said first processor for starting said second processor;

means responsive to a command from said first processor for holding said second processor;

means for allowing access to said bus means by said first processor when said first processor is active;

means for precluding access to said bus means by said second processor when said first processor is running;

means for allowing access to said bus means by said second processor when said second processor is active and;

means for precluding access to said bus means and said memory means by said first processor when said second processor is running.

7. The data processing system of claim 3 wherein said control means further comprises

means for monitoring processor interrupt conditions when said second processor is active,

means, responsive to said interrupt condition monitoring means, for holding said second processor when an interrupt condition is detected and

means for starting said first processor when a processor interrupt condition is detected by said interrupt condition monitoring means.

8. A data processing system comprising;

memory means;

first and second processors, said first processor including

means for running a first operating system,

means for processing all system input and output operations,

means for handling all system interrupts,

means for generating hold commands to said second processor and

means for generating start commands to said second processor,

and said second processor means including means for running a second operating system;

bus means, connected to said memory means, said first processor and said second processor, for transferring at least data and addresses between said first processor and said memory and between said second processor and said memory;

control means, connected to said first processor, said second processor and said bus means, said control means including

means for detecting an attempt by said second processor to perform an input or output operation,

means, responsive to said detecting means, for holding said second processor,

means, responsive to said detecting means, for starting said first processor,

means, responsive to a hold command from said first processor, for holding said second processor, and

means, responsive to a start command from said first processor, for starting said second processor.

9. The data processing system of claim 8, wherein said first processor also includes means for identifying certain portions of said memory as being protected from access by said second processor and wherein said control means also includes:

means for detecting an attempt by said second processor to access said protected portions of said memory,

means, responsive to said access detecting means, for holding said second processor and

means, responsive to said access detecting means, for starting said first processor.