Multiple task oriented processor

• US 4,591,976 A
• Filed: 06/17/1983
• Issued: 05/27/1986
• Est. Priority Date: 06/17/1983
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Webber, Douglas G., Schenck, George C.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Lee, Thomas
• Application Number:
  US06/505,165
• Time in Patent Office: 1,075 Days
• Field of Search: 364/423, 364/527, 364/200 MS File, 364/900 MS File
• US Class Current: 714/20
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

The computer system for missile guidance comprises five parallel processors interconnected by a global bus; with each processor having its own CPU, program memory, temporary memory, and two critical variable memories, interconnected by a local bus. The program memory and critical variable memory are hard MNOS to survive nuclear radiation. Each processor has its own cycle time, synchronized by a master clock. In each processor, the cycle has three phases for intercommunication, task processing, and critical variable storage. Thus the critical variables are stored only after task processing is completed.

Claims

1. A computer system comprising a plurality of processors operating in parallel and interconnected via a global bus, which may be subject to a short duration radiation event, each processor having its own cycle time, with synchronization by connection to a system clock, the system being partitioned by functional requirements into tasks that minimize both the number and rate of transfer of variables between processors;

wherein each of said processors comprises a central processing unit, a program memory comprising read only memory devices, a permanent storage memory comprising MNOS devices, a temporary storage memory comprising fast, volatile, bipolar random access memory devices, critical variable memory means comprising first and second memories of MNOS devices, and a local bus interconnecting the central processing unit and said memories, and isolating means coupled between the local bus and the global bus for providing isolation between them, there being means actuated in response to a program request with respect to a variable requiring access to another of said processors to initiate an automatic sequence to remove the isolation at said isolation means and to establish a linkage;

wherein said MNOS devices comprise memory field effect transistors which in the permanent storage memory are used with a slow write for long retentivity storage of constants including target constants and IMU calibration parameters, and in the critical variable memory means are used with approximately a 50-microsecond clear/write time to provide greater than one hour retentivity, the MNOS devices having relatively reduced thresholds, the memory field effect transistors having channels of a short length, harder oxides, and relatively shallow diffusions in device areas and bit lines, the processors further having digital logic circuits of a bipolar type selected from low power Schottky TTL and I² L;

each processor cycle having a sync time for synchronization with the other processors, followed in sequence by three activity phases, comprising a first activity phase for intercommunication, a second activity phase for task processing, and a third activity phase for critical variable storage;

wherein within each of said processors, said first and second memories respectively have first and second base addresses, there being means effective during normal processing for storage of critical variables from the temporary storage memory into the critical variable memory means during said third phase in which the storage alternates between the first and second memories on successive processor iterations by means for determining the base address used in the previous iteration and changing to the other, in which the critical variable resulting from each iteration are time tagged and this time is used to bracket the data stored by means for storing a first time value, then storing data, and then storing a last time value, the first and last time values being the same during a cycle provided no radiation event has been detected during the storage sequence;

means actuated in response to passage of one of said radiation events which causes loss of information in the temporary memory store to enter a recovery program, wherein the program includes means to determine whether data in the first or second memory is valid and which is most recent by means for comparing the first and last time values for the first memory, if they are not equal setting the base address to that of the second memory, and alternatively if they are equal to then compare the first and last time values for the second memory, if they are not equal setting the base address to that of the first memory, and alternatively if they are equal to then compare the first time values for the first and second memories and setting the base address to the one of the first and second memories for which the time value is greater, the data being read from the first or second memory of the critical variable memory means as determined by the base address setting and written into the temporary storage memory with the time tag of that point in time for which the data is valid, which allows the recovery, executive, or normal processing to account for the process downtime and to effect remedial action as required;

whereby the combination of time tag and base addressing eliminates any need for a separate pointer for the critical variable memory means.

2. The computer system according to claim 1, which includes junction isolated logic and memory technology, wherein burnout prevention relating to said radiation event includes power supply means in which current is limited to one ampere per IC for no more than one microsecond, and wherein V_cc is reduced to a level of less than on diode voltage drop or about 0.7 volt at room temperature to ensure that devices in latchup will recover.