Adaptive self-repairing processor array

• US 4,591,980 A
• Filed: 02/16/1984
• Issued: 05/27/1986
• Est. Priority Date: 02/16/1984
• Status: Expired due to Fees

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Huberman, Bernardo A., Hogg, Tad H.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/580,919
• Time in Patent Office: 831 Days
• Field of Search: 364/200 MS File, 371/11
• US Class Current: 712/16
• CPC Class Codes: G06F 11/1476 in neural networks
• CPC Class Codes: G06N 3/10 Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Abstract

An adaptive self-repairing processor array comprising a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix, each of said cells in the array having logic means and a memory for storing a memory state. The first row of the cells in the array forms a parallel input to the array. The last row of said cells in the array forms a parallel output from the array. The cells in the intermediate cells rows between the first and last rows are coupled to at least one cell in a previous cell row. The logic means in each cell computes a new data value based upon the input or inputs from such previous row cells and its present memory state. Each cell is further coupled to at least one cell in the subsequent row of cells. The computed new data value is provided as an output to the coupled cell or cells in the subsequent cell row. Each of the intermediate row cells are coupled to immediately adjacent neighbor cells of the same row to supply the new data value to these neighbor cells and correspondingly receive computed new data values from these same cells. The logic means in each cell compares the new data values received from such neighbor cells with its computed new value and accordingly updates its memory state based upon the results of the comparison.

Claims

1. An adaptive self-repairing processor array comprising a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix, each of said cells in said array having logic means and a memory for storing a memory state, the first row of said cells in the array forming a parallel input to the array, the last row of said cells in the array forming a parallel output from the array, the cells in the intermediate cell rows between said first and last rows coupled to at least one cell in a previous cell row, said logic means in each cell to compute a new data value based upon said input and its present memory state, said each cell coupled to at least one cell in a subsequent cell row, said new data value provided as an output to said subsequent cell row, each of said intermediate row cells coupled to immediately adjacent neighbor cells of the same row to supply said new data value to said neighbor cells and correspondingly receive new data values from said neighbor cells, said logic means in each cell to compare the new data values received from said neighbor cells with its computed new data value and accordingly update its memory state based upon the results of said comparison.

2. The adaptive self-repairing processor array of claim 1 wherein the updating of said memory state is accomplished only within a set range of values.

3. The adaptive self-repairing processor array of claim 1 wherein the values provided as output from said cells are accomplished only within a set range of values.

4. An adaptive self-repairing processor processor array comprising

a plurality of identical processing cells arranged in parallel orthogonal columns and rows to form a two dimensional matrix,

the first row of said cells in the array forming a parallel input to the array, each cell of said first row adapted to receive an input signal from a signal source,

subsequent rows of said cells coupled to immediate neighborhood cells in both orthogonal and diagonal directions relative to said parallel orthogonal rows and columns,

means in each of said cells to receive an input signal from said coupled cells in a previous cell row and from coupled neighbor cells in the same cell row,

means in each of said cells to transmit an output signal to coupled cells in a subsequent cell row and to coupled adjacent cells in the same cell row,

memory means in each cell to store a data value therein,

logic means to perform simultaneous iterative calculations in the cells of each row based upon said input signals wherein the cells of each cell row calculate new values based upon said input signals and its present memory value and compare the new value with new values attained by said coupled adjacent cells,

means to update the memory value in each of said cells to store said new value if the new value is different from the present memory value,

the last row of said cells in the array forming a parallel output from the array, said parallel output representative of a corresponding enhancement of the original signal source parallel input of said array regardless of any inappropriate changes to the instantaneous value of one or more of said array cells due to an abnormality of malfunction in any such affected array cells.

5. The adaptive self-repairing processor array of claim 4 wherein said cells further include

means in each of said cells to inhibit a change in said present memory value in a cell when such value has reached a predetermined limit.

6. A method of parallel processing of a plurality of input signals from a source, representative of a wave of data, to provide an enhancement to the values of said data wave based upon the difference in signal values between adjacent input signals of the data wave comprising the steps of

extending said input signals in parallel fashion through an orthogonal array of processor cells wherein cell rows are connected to some neighborhood cells of a previous cell row and to some neighborhood cells of a subsequent cell row and to some neighborhood cells of the same cell row and characterized in that said method relative to an observed cell in each cell row further comprises the steps of:

computing a new data value in the observed cell which has at least one input from a cell in a previous cell row,

comparing the new data value of the observed cell with the new data value of at least one adjacent neighbor row cell,

updating the present data value of the observed cell to the new value if the new data value is the greater or lesser of the compared new value of at least one adjacent neighbor row cell,

maintaining the present data value of the observed cell if the new data value is the same or not the greater or lesser of the compared new value of said at least one adjacent neighbor row cell,

outputting the new data value of the observed cell to at least one cell in a subsequent cell row.

7. The method of claim 6 including the step of

inhibiting any further change in the present value of the observed cell if the new data value is greater or smaller than a predetermined range of values.