Semiconductor memory

• US 4,592,022 A
• Filed: 07/19/1985
• Issued: 05/27/1986
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo, Ikuzaki, Kunihiko
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/756,707
• Time in Patent Office: 312 Days
• Field of Search: 365/189, 365/190, 365/230, 365/149, 365/182
• US Class Current: 365/149
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a memory cell array occupying an area of a semiconductor substrate, said area of the array having opposite ends;

said memory cell array including a plurality of data lines which extend from one of said opposite ends of said area of the array to the other of said opposite ends, a plurality of word lines which extend in a direction traversing the data lines, and a plurality of memory cells arrayed in said memory cell array in association with said data and word lines;

each of said memory cells including a P-channel MOS transistor and a capacitive element which is coupled to one of said data lines through the source-drain path of said P-channel MOS transistor, the gate of said P-channel MOS transistor being coupled to one of said word lines;

a plurality of sense amplifiers including a plurality of pairs of N-channel transistors and a plurality of pairs of P-channel transistors;

said plural pairs of N-channel transistors being formed in said semiconductor substrate at said one end of said area of the array, each pair of said N-channel transistors being cross-coupled to each other and being coupled to a pair of adjacent ones of said data lines;

said plural pairs of P-channel transistors being formed in said semiconductor substrate at said other end of said area of the array, each pair of said P-channel transistors being cross-coupled to each other and being coupled to a pair of adjacent ones of said data lines so as to construct each of said sense amplifiers together with said cross-coupled pair of N-channel transistors associated with the same pair of data lines.

2. A semiconductor memory according to claim 1, wherein each of said sense amplifiers further comprises means coupled in series with said cross-coupled pair of N-channel transistors and said cross-coupled pair of P-channel transistors to control operations of the respective cross-coupled pairs.

3. A semiconductor memory according to claim 2, wherein said means is constructed of an N-channel MOS transistor which is connected in series with said cross-coupled pair of N-channel transistors, and a P-channel MOS transistor which is connected in series with said cross-coupled pair of P-channel transistors.

4. A semiconductor memory according to claim 1, wherein said P-channel transistors of said memory cells are formed in a first N-type well region which is formed in the semiconductor substrate of a P-type, and said plural pairs of P-channel transistors of the sense amplifiers are formed in a second N-type well region which is formed in said P-type semiconductor substrate.

5. A semiconductor memory according to claim 1, wherein said P-channel transistors of said memory cells and sense amplifiers are formed in a common N-type well region which is formed in a common N-type well region which is formed in the semiconductor substrate of a P-type.

6. A semiconductor memory formed in a semiconductor integrated circuit comprising:

an array of memory cells, wherein each memory cell of said array includes a series connection of a P-channel MOS transistor and a capacitive means;

a plurality of data lines arranged in connection with said array and extending in parallel with each other, each of said data lines being coupled to the series connections of corresponding ones of said memory cells of said array;

a plurality of word lines arranged in connection with said array and extending in parallel with each other in a direction traversing said data lines, each of said word lines being coupled to the gates of the MOS transistors of corresponding ones of said memory cells of said array; and

a plurality of sense amplifiers, each of said sense amplifiers being coupled to a pair of adjacent ones of said data lines;

said each sense amplifier including a pair of N-channel MOS transistors disposed on a first side of said array, and a pair of P-channel MOS transistors disposed on a second side of said array opposite to said first side, each of said P-channel and N-channel transistors of the sense amplifier having a gate, a drain and a source;

each gate of said pair of N-channel transistors being cross-coupled to the drain of the other of said pair of N-channel transistors, the drains of said pair of cross-coupled N-channel transistors being respectively coupled to said pair of data lines on said first side of said array; and

each gate of said pair of P-channel transistors being cross-coupled to the drain of the other of said pair of P-channel transistors, the drains of said pair of cross-coupled P-channel transistors being respectively coupled to said pair of data lines on said second side of said array.

7. A semiconductor memory according to claim 6, wherein said P-channel transistors of said memory cells are formed in a first N-type well region which is formed in a P-type semiconductor substrate, and said P-channel transistors of said sense amplifiers are formed in a second N-type well region which is formed in said P-type semiconductor substrate in the vicinity of said first N-type well region.

8. A semiconductor memory according to claim 6, wherein said P-channel transistors of said memory cells and sense amplifiers are formed in a common N-type well region which is formed in a P-type semiconductor substrate.