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Semiconductor memory

  • US 4,592,022 A
  • Filed: 07/19/1985
  • Issued: 05/27/1986
  • Est. Priority Date: 05/13/1981
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

  • a memory cell array occupying an area of a semiconductor substrate, said area of the array having opposite ends;

    said memory cell array including a plurality of data lines which extend from one of said opposite ends of said area of the array to the other of said opposite ends, a plurality of word lines which extend in a direction traversing the data lines, and a plurality of memory cells arrayed in said memory cell array in association with said data and word lines;

    each of said memory cells including a P-channel MOS transistor and a capacitive element which is coupled to one of said data lines through the source-drain path of said P-channel MOS transistor, the gate of said P-channel MOS transistor being coupled to one of said word lines;

    a plurality of sense amplifiers including a plurality of pairs of N-channel transistors and a plurality of pairs of P-channel transistors;

    said plural pairs of N-channel transistors being formed in said semiconductor substrate at said one end of said area of the array, each pair of said N-channel transistors being cross-coupled to each other and being coupled to a pair of adjacent ones of said data lines;

    said plural pairs of P-channel transistors being formed in said semiconductor substrate at said other end of said area of the array, each pair of said P-channel transistors being cross-coupled to each other and being coupled to a pair of adjacent ones of said data lines so as to construct each of said sense amplifiers together with said cross-coupled pair of N-channel transistors associated with the same pair of data lines.

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