Multi-channel implantable neural stimulator

• US 4,592,359 A
• Filed: 04/02/1985
• Issued: 06/03/1986
• Est. Priority Date: 04/02/1985
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Galbraith, Douglas C.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/719,231
• Time in Patent Office: 427 Days
• Field of Search: 128/419 R, 128/419 E, 128/419 C, 128/419 G, 128/421-422
• US Class Current: 607/57
• CPC Class Codes: A61N 1/36038 Cochlear stimulation

Abstract

A combination of a transmitter and implantable receiver are disclosed wherein data is conveyed from transmitter to receiver utilizing a data format in which each channel to be stimulated is adapted to convey information in monopolar, bipolar or analog form.

The data format includes two types of code words: transition words in which one bit is assigned to each channel and can be used to create monopolar pulsatile or bipolar pulsatile waveforms; and amplitude words which can create analog waveforms one channel at a time.

An essential element of the output system is a current source digital to analog converter which responds to the code words to form the appropriate output on each channel. Each output is composed of a set of eight current sources, four with one polarity of current and the other four with the opposite polarity of current. In each group of four, the current sources are binarily related, I, 2I, 4I and 8I. In this arrangement each channel can supply 16 amplitudes times two polarities of current; meaning 32 current levels. This channel is simply a 5-bit digit to analog converter.

The output circuitry contains charge balance switches. These switches are designed to recover residual charge when the current sources are off. They are also designed to current limit during charge recovery if the excess charge is too great so that they do not cause neural damage.

Each channel charge balances (will not pass DC current or charge) and charge limits to prevent electrode damage and bone growth. The charge balancing is performed by the charge balancing switches and by the blocking capacitor. The charge limiting is performed by the blocking capacitor only.

The charge level on each channel is defined using a switch network ladder which combines a plurality of parallel connected switches; closure of each switch doubles the current level handed off from the previous switch.

Claims

1. A neural stimulator comprising a transmitter, an implantable receiver and means for coupling the output of said transmitter to said receiver, said receiver including a plurality of output channels to the nerves of the wearer, said receiver including means for simultaneously addressing each of said channels in monopolar or bipolar mode, or alternatively in analog mode to stimulate said nerves.

5. A stimulator as claimed in claim 1 further comprising a multi-electrode stimulus array connected to the output channels of the stimulator.

6. A stimulator as claimed in claim 5 including means for establishing transition words for defining a binary state on each of said channels, and means for creating amplitude words for defining an analog signal on any of said channels.

7. A stimulator as claimed in claim 5 wherein said means for establishing a transition word simultaneously address all of said plurality of channels.

8. A stimulator as claimed in claim 7 wherein said means for establishing a transition word comprise means for transmitting an unused bit sequence for synchronizing all of said channels.

9. A stimulator as claimed in claim 7 wherein said means for establishing a transition word cooperate with a polarity bit from the means for establishing an amplitude word to provide monopolar or bipolar stimulation on each of said channels.

2. A stimulator as claimed in 1 wherein said receiver includes a current source device coupled to each of said channels, said current source device comprising a switch network, the number of closed switches selectively defining the charge and current envelope on any channel.

3. A stimulator as claimed in claim 2 further comprising a charge balancing switch cooperating with each of said current source devices and blocking capacitors for eliminating charge imbalance into the electrode channels.

4. A stimulator as claimed in 1 wherein said addressing means further comprise means for defining a quantized analog current waveform on any of said channels.