Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide

• US 4,593,302 A
• Filed: 08/18/1980
• Issued: 06/03/1986
• Est. Priority Date: 08/18/1980
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lidow, Alexander, Herman, Thomas
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US06/178,689
• Time in Patent Office: 2,115 Days
• Field of Search: 357/23, 357/41, 357/59, 357/20
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.

Claims

1. A high current MOSFET having low forward resistance comprising a semiconductor chip having first and second parallel surfaces;

said chip having a body portion which is relatively lightly doped with impurities of a first conductivity type;

said body portion extending from said first surface for at least a portion of the thickness of said chip;

a plurality of local regions of a second conductivity type distributed over and extending into said first surface of said chip;

a plurality of source regions of said first conductivity type extending into respective ones of said plurality of local regions and having a depth less than the depth of their said respective local region and an outer periphery which is interior of and spaced by a fixed distance from the periphery of said local region at said first surface, thereby to define short conduction channels capable of inversion;

each of said plurality of local regions being spaced from one another at said first surface by a symmetric mesh of said body portion;

a mesh-shaped gate insulation layer extending over said mesh between said local regions and overlapping said short conductive channels surrounding said local regions;

a mesh-shaped gate electrode disposed atop said gate insulation layer;

a vertical conductive region of said first conductivity type extending from beneath said gate insulation layer and between adjacent local regions and toward said second surface;

a common source electrode connected to each of said source regions and to each of said local regions;

said common source electrode extending over said first surface; and

a drain electrode connected to said second surface;

said vertical conductive region having a higher doping concentration than that of said body portion for a depth below said first surface which is less than the depth of said local regions;

said doping concentration in said vertical conductive region having a constant value laterally across said first surface beneath said insulation layer.

2. The MOSFET of claim 1 wherein the doping concentration beneath said gate insulation layer decreases with depth below said first surface, and has a constant lateral concentration at any given depth.

3. The MOSFET of claim 1 wherein said gate insulation layer is an oxide and wherein said gate electrode atop said oxide is polysilicon.

4. The MOSFET of claim 1 wherein said vertical conductive region has a depth beneath said first surface of about one micron.

5. The MOSFET of claim 1 wherein said local regions and said source regions have corresponding peripheries which are polygonal.

6. The MOSFET of claim 1 wherein said local regions and said source regions have corresponding peripheries which are hexagonal.

7. The MOSFET of claim 1 wherein said local regions have a deep central region and a shallow outer periphery;

said source regions overlying said shallow outer peripheries of their said respective local regions.

8. The MOSFET of claim 1 wherein said chip has a floating guard ring of said second conductivity type extending around the outer periphery of said first surface.

9. The MOSFET of claim 1 wherein at least one elongated gate contact is deposited on said mesh-shaped gate electrode for making contact to said mesh;

said elongated gate contact being coplanar with said source electrode and electrically insulated therefrom.

10. A high power MOSFET device having a large number of parallel-connected individual FET devices closely packed into a relatively small area comprising:

a thin wafer of monocrystalline semiconductor material having first and second spaced, parallel surfaces;

at least a first portion of the thickness of said wafer which extends from said first surface having a resistivity of a value characterized by an epitaxially deposited N- or P- region and being of one of the N or P conductivity types;

a plurality of symmetrically disposed, laterally distributed hexagonal regions, each extending into said first portion of said wafer for given depths and extending to said first surface;

said hexagonal regions spaced from one another by a symmetric hexagonal lattice of the material of said first portion;

each side of each of said hexagonal regions being parallel to and adjacent the side of another of said hexagonal regions;

a respective hexagonal annular source region of the other of the conductivity types formed in the outer peripheral regions of said each of said hexagonal regions and extending downward from said first surface;

the outer rim of each of said annular source regions being annularly spaced from the outer periphery of its said respective hexagonal region to form an annular channel between each said annular source region and the adjacent said hexagonal lattice of the material of said first portion of said wafer which is diposed between said hexagonal regions;

a single common source electrode formed in said first surface and connected to each of said source regions and to the center of each of said hexagonal regions at said first surface;

a single drain electrode connected to said second surface of said wafer;

an insulation layer means on said first surface and overlying said hexagonal lattice of material disposed between said hexagonal regions and said annular channels; and

a gate electrode atop said insulation layer means and operable to control the formation of an inversion layer in said annular channels;

said hexagonal lattice having an increased doping concentration at said first surface;

said doping concentration having a constant value laterally across said hexagonal lattice at said first surface.

11. The MOSFET device of claim 10 wherein said doping concentration in said hexagonal lattice decreases with depth below said first surface, and has a constant lateral concentration at any given depth.

12. The MOSFET device of claim 10 or 11 wherein said gate electrode is of polysilicon material.

13. The MOSFET device of claim 10 or 11 which includes more than 1,000 individual parallel-connected FET devices formed in said wafer, which have a width less than about 1 mil.

14. The MOSFET device of claim 10 or 11 wherein the portions of said hexagonal lattice which extends from said first surface for a depth less than the depth of said hexagonal regions has a relatively high conductivity compared to the conductivity of said first portion of said wafer.