Time-programming apparatus

• US 4,594,007 A
• Filed: 12/20/1983
• Issued: 06/10/1986
• Est. Priority Date: 04/20/1982
• Status: Expired due to Fees

• Current Assignee: Westdeutsche Elektrogeratebau GmbH
• Original Assignee: Westdeutsche Elektrogeratebau GmbH
• Inventors: Brandenberg, Winfried
• Primary Examiner(s): Miska, Vit W.
• Application Number:
  US06/571,550
• Time in Patent Office: 903 Days
• Field of Search: 368/10-12, 368/28-29, 368/82-84, 368/250, 368/251, 368/107-113, 340/309.15, 340/309.4, 340/310 A, 364/569
• US Class Current: 368/10
• CPC Class Codes: G04G 15/006 for operating at a number of different times cigar or cigarette receptacles or boxes with means for limiting the frequency of smoking A24F15/005

Abstract

A time-programming apparatus comprises a central processor which includes at least one recording/readout working memory having addressable registers, computing means with at least one logic circuit connected to the working memory for processing output signals therefrom, and at least one program memory with associated program counter connected to the logic circuit for the generation and distribution of function signals for the central processor. The apparatus further comprises a luminous digital display connected to the processor and divided into subregions with respective display fields for alphanumeric display, input means including manually actuatable keys and switches assigned to the display fields, and output means for selective actuation of a load to be operated, the input and output means being connected to the central processor and all including the luminous display, with a wall provided therefor, being contained in a common housing. Power means in the housing supplies electric power to the central processor, the input means being so connected to the processor as to define hierarchical functioning and including first and second function-selection means and a further selection means.

Claims

1. An electronic time programming apparatus comprising:

a central processor including;

at least one recording/readout working memory having addressable registers,

computing means including at least one logic circuit connected to said recording/working memory for processing output signals therefrom, and

at least one program memory with an associated program counter connected to said logic circuit for the generation and distribution of function signals for said central processor;

a luminous digital display connected to said central processor and divided into subregions with respective display fields for alphanumeric display;

input means including manually actuatable keys and respective switches operated by said keys and assigned to the respective display fields and arranged in groups in respective subregions, said input means being connected to said central processor;

output means connected to said central processor and having a plurality of load circuits with respective channels for the selective actuation of a respective load to be operated by said apparatus;

a common housing for said central processor, said display, said input means and said output means and having a wall provided with said display; and

power means in said housing for supplying electrical power to said central processor, said input means being so connected to said central processor to define hierarchical functioning and including;

(a₁) first function selection switch means forming part of said input means and having keys for selecting between ON and OFF of respective ones of said channels for respective ones of said load circuits of said output means and between automatic (AUT) and control (STEL) modes in which, respectively, the automatic operation of the selected channels and the setting of inputs for said channels can be effected,

(a₂) second function selection switch means forming part of said input means and having keys for enabling said input means to key into said central processor an actual time of day (UHR) setting, a switch-ON time setting (EIN) for switching on a selected channel, a switch-OFF time setting (AUS) for switching off a respective channel, and an automatic operation setting (AUT) to enable said settings to be changed only upon both the initial operation of said first function selection means and keys for said settings of said second function selection means, and

(a₃) further selection means including single keys each for the selection of days of the week, hour (h) and minute (m) to form the respective time settings, switch-ON and switch-OFF time input keys for registering the respective time settings and for assignment thereof to respective switching channels to input the registered time setting for the respective channels in said central processor only upon actuation of corresponding keys of said first and second function selection means and of further selection means, each of said keys of said further selection means incrementing the respective setting while it is depressed, said input means and said central processor being constructed and arranged so that signal groups for said switching ON and switching OFF times and an associated channel are transferred from intermediate memories to said central processor in totality as data packages, each data package being applicable to corresponding inputs and outputs of said program and working memories by said computer means.

2. The apparatus defined in claim 1 wherein said display subregions are provided with display elements for:

signals assigned to the respective time settings,

signals assigned to the selected switching channels together with indicia representing the selected state thereof, and

signals for the display of pulses representing seconds by flashing.

3. The apparatus defined in claim 1 wherein said central processor working memory has separately addressable registers assignable in groups, said program memory and said working memory being provided with a part-programming memory for a half data package with a clock time data and switch-ON and switch-OFF and channel data and spacially separated from said working memory, at least one auxiliary register forming part of said program memory and said working mem0ory for receiving a complete data package with switch-ON and switch-OFF time data including data for days of the week and switching channels, and said memories including separately addressable further intermediate memories in said working memory for clock time data for switch-ON and switch-OFF time data for, days of the week data, for switching channel data and for actual state data of the respective channel indicating whether the same is switched on or off and means for selectively connecting said memories to each other, to said input means and to said display.

4. The apparatus defined in claim 1 wherein said program has a multiplicity of cells having outputs, said outputs of said cells of said programming memory being applied to respective inputs of a logic interconnection subassembly with respective logic circuit networks applying an output signal to the input of an AND-gate, another input of which is coupled to said programming memory, an output of said AND-gate being connected so that incomplete data as to a time setting triggers a flash command signal to each display element of an unoccupied subregion of said display associated with the respective time setting.

5. The apparatus defined in claim 4 wherein said logic circuit networks are so connected and arranged that incompatible conditions are signalled to said display flashing of signals representing incompatibly occupied memory data cells.

6. The apparatus defined in claim 3 wherein outputs of a first partial data package of said program memory and readout outputs of a second partial data package from said recording readout working memory are connected to and addressed to data packages associated with the same channel through a comparator stage in an increasing sequence from one switch-ON partial data package to the next switch-ON partial data package by means of an addressing counter incremented each time by one, means for continously incrementing the addressing counter until a third partial data package of the working memory is greater than the first partial data package of the programming memory, said comparator having an output, and means responsive to the output of said comparator for blocking transfer of data into said memory under a first set of conditions and releasing a respective complete data package from the programming memory into the working memory in a second set of conditions, the first set of conditions comprising at least one of the following:

equality of the first and fourth partial data packages of the programming memory, equality of the first and the second partial data packages of the programming memory, and equality of the fourth and third partial data packages of the programming memory and the relationship between fifth and fourth data packages of the working memory, said second set of conditions comprising a positive difference between at least one of the following;

the first switch-ON and the second switch-ON partial data packages, and the fourth switch-OFF and the third switch-OFF partial data packages.

7. The apparatus defined in claim 3, further comprising means for selectively altering the contents of a selected one of said subregions for at least one of said channels or days independently of the other subregions.

8. The apparatus defined in claim 3, further comprising means connected to said central processor for altering data of a selected one of said subregions by one value step at a time by a single actuation of one of said keys and in a direction represented by the actuation of another of said keys defining algebraic addition.

9. The apparatus defined in claim 3, further comprising means including a logic stage for canceling the effect of a previously actuated function selection key.

10. The apparatus defined in claim 3 wherein an input memory is provided for the day of the week (TAG) in the form of a shift register connected in said central processor by a logic stage capable of confirmation of multiple storage of day data.

11. The apparatus defined in claim 3 wherein said switches include channel selection switches assigned to said channels and settable independently of and outranking the function keys.

12. The apparatus defined in claim 3, further comprising a clear key forming part of said input means and connected to said central processor for canceling the electrical effect of the keys actuated in an immediately preceding step and for the erasure of a corresponding section of said display.

13. The apparatus defined in claim 3 wherein said function selection keys are provided in circuit with a shift register device for switching them over from the control circuit of a respective function selection to another in the sequence UHR-EIN-AUS-AS 1 . . . -AUT-UHR by successive actuation of at least one of said keys.

14. The apparatus defined in claim 3, further comprising means forming part of said central processor and including a timing circuit for resetting the function selection keys after the lapse of a presettable time interval if none of the function setting keys is actuated within this interval.

15. The apparatus defined in claim 3 wherein said keys and switches are provided on a panel of said housing in a matrix consisting of groups spaced to reflect their functions.

16. The apparatus defined in claim 3 wherein each function selection key is connected to an AND gate and a flip-flop and provided with a clock pulse source so that each time a function key is actuated the flip-flops of all other such keys are reset.

17. The apparatus defined in claim 3 wherein said central processor includes an electric clock having an output signal connected via a respective command gate to each input of a plurality of said logic circuit together with output signals of intermediate memories representing data sections of actual time of day, switch-ON and switch-OFF times, week days and switching channels, the other inputs of each of said and gates being controlled by an output signal of a flip-flop connected to a switch associated with the AUT key.

18. The apparatus defined in claim 3 wherein bistable switches are provided for each of said keys for locking the state thereof in one of two operating conditions.

19. The apparatus defined in claim 3 in which a two-position switch having a set position (STEL) and an automatic position (AUT) is provided in a control circuit of each of the function selection keys with the exception of the AUT key for blocking the input of the respective function selection key upon activation of said AUT key.

20. The apparatus defined in claim 3 wherein said input means includes a clear key (CLE) having a signal circuit including an OR gate having an output applied to a resetting input of respective monoflops in signal circuits of respective setting keys of said input means and a Q output signal of a time delay controlled monostable flop member is connected in respective resetting circuits of flip-flops of signal circuits of the respective function key, an input of said flop member being commanded by an OR gate which is input controlled by Q output signals of said flipflops.

21. The apparatus defined in claim 1 wherein said central processor includes a microprocessor formed with said logic circuit and at least part of said memories.

22. The apparatus defined in claim 21 wherein said display has liquid crystal display elements and is formed in a compact semiconductor unit technologically integrated with said microprocessor.

23. The apparatus defined in claim 22 wherein said semiconductor unit is mounted on a circuitboard held in said housing between an upper casing and a lower casing part, said upper casing part having a window through which said display fields can be viewed, said keys being provided adjacent said window on said upper casing part, said casing parts having matched wall edges and being provided with means for securing them together to form said housing.

24. The apparatus defined in claim 23 wherein said circuitboard is reinforced by further circuitboards positioned at right angles to the first mentioned circuitboard.

25. The apparatus defined in claim 23 wherein said lower casing part has grooves at two opposite side walls for holding it to said upper casing part.

26. The apparatus defined in claim 1 wherein said keys are formed with fingers composed of an elastomeric electrical conductive material, each finger having a neck of rectangular cross section, said keys being guided through a respective rectangular perforation in said wall of said housing and cooperating with conducting tracks within said housing.

27. The apparatus defined in claim 1 wherein said keys are provided in operating and setting fields adjusting said display fields, said display fields and said operating and setting fields having adjacent sides of approximately equal length such that both form an elongated rectangul on said wall with a side ratio of two to one.