Current mirror digital to analog converter

• US 4,594,577 A
• Filed: 09/24/1982
• Issued: 06/10/1986
• Est. Priority Date: 09/02/1980
• Status: Expired due to Term

• Current Assignee: AMI Semiconductor Inc (ON Semiconductor Corporation)
• Original Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Inventors: Mao, Roger A.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/650,120
• Time in Patent Office: 1,355 Days
• Field of Search: 340/347 DA, 340/347 M, 340/347 AD, 340/347 CC, 375/30
• US Class Current: 341/135
• CPC Class Codes: G10L 15/12 using dynamic programming techniques, e.g. dynamic time warping [DTW]
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

An integrated circuit digital to analog converter comprised of MOS current mirrors and utilizing additional MOS devices to provide transmission gates and control means. Each transmission gate 36 is connected to a source of digital data to be converted and the mirroring device for each transmission gate 36 has a channel width with some predetermined proportional relationship to the channels of input transistors 12 and mirroring output MOS transistors 14 to 44 with the input transistor 12 connected to a constant current source, the total output mirroring current of the output mirroring transistors is in quantised analog form and varies according to the cumulative currents from the mirroring MOS transistors as the transistors are activated. The invention may be embodied in linear multiplying, non-linear and companding converters.

Claims

1. A nonlinear current mirror digital to analog converter for providing an analog output signal from binary data signals in accordance with the "μ

225" law, said binary data signals including a first set of signals defining a chord and a second set of signals defining a step, said converter comprising;

a first input transistor connected to a current source;

a second transistor, the current flowing through said second transistor being proportional to the current from said current source;

a first set of linear logic gates, each having a first input lead connected to said current source and a second input lead connected to a data source for designating steps of the "μ

255" law curve, each gate within said first set of linear logic gates providing an output signal on an output lead;

a first set of transistors, each corresponding to one of said linear logic gates, the current through each transistor within said said first set of transistors being proportional to the current through said first transistor in response to the output signal from said associated linear logic gate;

a second set of transistors;

a second set of linear logic gates, each linear logic gate within said second set having a first digital input lead and a second digital input lead for receiving data signals designating the chords of the "μ

255" law curve, each of said logic gates within said second set of logic gates corresponding to a transistor within said second set of transistors, each transistor within said second set of transistors conducting a current proportional to the current from said current source when the signal at the first digital input lead of said corresponding linear logic gate is in a first binary state, each transistor within said second set of transistors conducting a current proportional to the total amount of current through said first set of transistors when the signal present at the second digital input lead of said corresponding logic gate is in said first binary state; and

an output lead for conducting an amount of current equal to the total current flowing through said second set of transistors.

2. The nonlinear current mirror digital to analog converter of claim 1 wherein each of said first series of linear logic gates are linear AND gates comprised of one pair of MOSFET devices, said pair of MOSFET devices connecting said first input lead to said output lead in response to said second input lead being in said first binary state, said linear logic gate within said first series of linear logic gates connecting said output lead to a first reference voltage in response to said second input lead being in a second binary state opposite said first binary state;

and

wherein the linear logic gates within said second set of linear logic gates include a first analog input lead connected to said first set of transistors and a second analog input lead connected to said second transistor, and an output lead, said first analog input lead being connected to said output lead in response to the signal at said first digital input lead being in said first binary state, said second analog input lead being connected to said input lead in response to the signal at said second digital input lead being in said first binary state, said output lead being connected to a second reference voltage in response to the signals at said first and second digital input leads being in said second binary state.

3. The digital to analog converter of claim 1 wherein said first series of linear logic gates includes four linear logic gates for receiving input signals corresponding to a step and a fifth linear logic gate for receiving a digital signal corresponding to a sign bit.

4. A digital to analog converter for providing an analog output signal from binary data signals in accordance with the "μ

255" law comprising;

means for providing a first current;

means for receiving a first set of binary data bits indicative of a step value;

a first set of transistors having a first channel conductivity type, each of said transistors being associated with one bit of said first set of binary data bits and conducting a current proportional to said first current in response to said one bit;

means for receiving a second set of binary data bits indicative of a chord value; and

a second set of transistors having a second channel conductivity type opposite said first conductivity type, each transistor within said second set being associated with two bits of said second set of binary data bits, each transistor within said second set of transistors conducting a current proportional to said first current in response to a first of said two associated bits, each transistor within said second set of transistors conducting a current proportional to the current through said first set of transistors in response to a second of said two associated bits.