Synchronous receiver

• US 4,594,727 A
• Filed: 01/05/1983
• Issued: 06/10/1986
• Est. Priority Date: 01/05/1983
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Universal Data Systems Incorporated
• Inventors: Pierce, O. Leon
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/455,855
• Time in Patent Office: 1,252 Days
• Field of Search: 375/10, 375/52, 375/82, 375/83, 375/99, 375/101, 375/84, 375/85, 375/86, 375/95, 375/97, 330/252, 330/260, 330/261, 328/162, 371/5, 371/6, 340/347 AD, 329/50, 329/110, 329/112, 455/205
• US Class Current: 375/329
• CPC Class Codes: H04L 27/2276 using frequency multiplication or harmonic tracking

Abstract

A synchronous receiver for receiving a phase shift modulated signal having binary data at a clock rate occurring within a baud interval. The synchronous receiver provides multiple estimates of the signal phase during selected portions of the baud interval, wherein the resulting phase values are averaged to provide a data output of low error rate and high reliability. The synchronous receiver of the present invention independently recovers the carrier and clock signals by separate digital phase-locked loops, wherein the resulting signals are used by the synchronous detector portion to recover the digital data. Moreover, the data acquisition time is improved by variable bandwidth characteristics of the phase locked loops.

Claims

1. A synchronous receiver including:

means for receiving a carrier signal comprising a phase-shift modulated signal with binary data having a baud rate;

carrier recovery means providing a recovered carrier signal;

absolute phase comparison means providing an absolute phase output signal related to said binary data and measured by the phase difference between the received phase-shift modulated signal and said recovered carrier signal, comprising;

a multiple sample means providing a plurality of sampled absolute phase signals; and

sample average means providing said absolute phase output according to an average of said sampled absolute phase signals.

2. The synchronous reciever of claim 1, further comprising:

a data transition detector responsive to said baud rate providing a control signal indicating a non-transitional period of said binary data, wherein;

said absolute phase comparison means provides said absolute phase output signal when enabled by said control signal.

3. The synchronous receiver of claim 1 wherein said baud rate has a corresponding baud interval,

said phase comparison means providing said absolute phase output signal for a predetermined duration about the center of said baud interval.

4. The synchronous receiver of claim 3 wherein said predetermined duration comprises 50 percent of said baud interval.

5. The synchronous receiver of claim 1 wherein said plurality of sampled absolute phase signals comprise signals having a duty cycle related to said absolute phase;

said sample average means comprises a digital integrator accummulating each of said plurality of sampled absolute phase signals;

wherein said sample average means converts each said duty cycle to a respective pulse signal having a related number of cycles; and

said sample average means receiving said respective pulse signals providing a cumulative total over a baud interval corresponding to said baud rate.

6. The synchronous receiver of claim 5 wherein said carrier is differentially phase modulated by said binary data, said receiver further including clock recovery means providing a recovered clock signal according to said baud rate and a differential phase detector means comprising:

a reference phase memory storing a signal corresponding to said first absolute phase output signal according to said recovered clock signal;

a differential phase comparator comparing the next subsequent absolute phase output signal to said signal corresponding to said first absolute phase output signal providing a differential phase output corresponding to said data signal, wherein

said reference phase memory stores said next subsequent absolute phase output signal after said differential phase output is produced.

7. The synchronous receiver of claim 6 wherein said reference phase memory comprises a presettable counter having a plurality providing a number of states corresponding to the number of data states possible within each baud interval;

said absolute phase comparison means comprise a plurality of multiple sample means each receiving an output of said reference phase memory counter and said received phase shift modulated signal providing a respective absolute phase output signal;

a resettable counter having a plurality of outputs providing a number of data states possible within each baud interval;

said counter being incremented by a clock signal;

a logical comparator indicating the logical equivalence of said absolute phase comparator output and said resettable counter output, said differential phase output corresponding to the number of pulses required by said resettable counter to form said logical equivalence; and

means to reset said resettable counter after said logical equivalence.

8. The synchronous receiver of claim 7, further comprising:

data quality measurement means connected to said sample average means providing a valid data signal.

9. The synchronous receiver of claim 8 wherein:

said data quality measurement means includes a data error counter, said valid data signal being produced at said data error counter output upon a predetermined number of consecutive low quality data signals produced by said sample average means.

10. The synchronous receiver of claim 1 wherein said carrier recovery means comprises a carrier phase-locked loop, wherein said recovered signal is phase-locked to the received phase shift modulated signal.

11. The synchronous receiver of claim 10 wherein said carrier phase locked loop comprises a digital second order phase locked loop.

12. The synchronous receiver of claim 11 wherein said carrier phase locked loop comprises a variable bandwidth phase locked loop.

13. The synchronous receiver of claim 1 further comprising:

first phase shift means receiving said received signal producing a quadrature pair recieved signal;

second phase shift means producing a quadrature pair recovered carrier signal; and

wherein said absolute phase comparison means produces a plurality of measured phase differences, said synchronous receiver further comprising;

second multiple sample means;

said sample average means also receiving said multiple sample means output.

14. The synchronous receiver of claim 5 wherein:

said digital integrator comprise at least one digital counter,

said digital counter being incremented by a clock signal when enabled by said baud rate control signal and a coincidence of at least one of a quadrature pair received signal and at least one of a quadrature pair recovered carrier signal, said digital counter having an output which, at the end of the time interval of the baud rate control signal corresponds to an average of the measured phase difference during the baud rate time interval.

15. The synchronous receiver of claim 14 wherein:

said absolute phase comparison means includes the number of integrating digital counters which in combination correspond to the number of unique integral phase shift data values of the received phase shift modulated signal, said absolute phase comparison means further includes;

an integer phase shift means to shift the recovered carrier frequency by integer values of phase;

an integer comparator means producing a phase time signal when the recovered carrier frequency is shifted by the number of integer phase shifts;

means to determine the number of integer phase shifts provided by integer phase shift means to produce a phase true signal producing a number output, wherein said number output corresponding to the data value of phase shifts of the received phase shift modulated signal.

16. The synchronous receiver of claim 15 wherein:

said received signal has four integer phase shift data values, each being 90°

; and

said received signal and said regenerated carrier have a phase shift difference of 45°

.

17. The synchronous receiver of claim 15 further comprising:

carrier quality determination means including a coincidence means connected to said integrating digital counters providing a counter coincidence output corresponding to the mutual coincidence of the states of the integrating digital counters; and

a hysterisis means producing a quality output enable signal receiving said coincidence output to provide a predetermined number changes of said coincidence output before said quality output, enable signal changes.

18. The syncronous receiver of claim 1, further comprising a self-adjusting wave forming means receiving a sinusoidal signal and providing said received signal comprising:

amplifier means having an inverting and non-inverting input and an output providing said digital received signal;

reference voltage means corresponding to a voltage at the mid-point of the amplifier output;

a first resistor connected to said amplifier output and said non-inverting input;

a second resistor connected to said non-inverting input and said reference voltage means;

a third resistor connected to said amplifier output and said inverting input; and

a capacitor connected to said inverting input and said sinusoidal signal wherein the product of the values of the third resistor and the capacitor are substantially greater than the period of the sinusoidal signal.

19. A self-adjusting wave forming means receiving an analog signal having a periodicity and forming a digital received signal having the same periodicity as said analog signal, said wave forming means comprising:

amplifier means having an inverting and non-inverting input and an output providing said digital received signal;

reference voltage means corresponding to a voltage at the mid-point of the amplifier output;

a first resistor connected to said amplifier output and said non-inverting input;

a second resistor connected to said non-inverting input and said reference voltage means;

a third resistor connected to said amplifier output and said inverting input; and

a capacitor connected to said inverting input and said analog signal wherein the product of the values of the third resistor and the capacitor are substantially greater than the period of the analog signal.

20. A method of detecting data signals in a digitally modulated carrier, comprising the steps of:

multiple data sampling the signal over a sample period corresponding to the open area of the eye pattern to sychronously detect said data signals;

averagaing the data sample over the sample period;

recovering a carrier signal; and

phase-locking said recovered carrier signal over a period corresponding to the open area of the eye pattern.

21. The method of claim 20, further including the steps of generating a recovered clock signal, and

phase locking said recovered clock signal over a period corresponding to the open area of the eye pattern.