Teletext decoder using a common memory

• US 4,595,951 A
• Filed: 11/29/1983
• Issued: 06/17/1986
• Est. Priority Date: 11/29/1983
• Status: Expired due to Term

• Current Assignee: RCA Corporation (General Electric Company)
• Original Assignee: RCA Corporation (General Electric Company)
• Inventors: Filliman, Paul D.
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/556,353
• Time in Patent Office: 931 Days
• Field of Search: 358/141, 358/142, 358/146, 358/147, 358/181, 358/903, 364/200, 364/900
• US Class Current: 348/468
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A teletext decoder extracts digital information from a video signal for displaying graphics and textual information embedded in the video signal. The decoder includes a prefix processor responding to user supplied commands for selecting and storing the pertinent embedded information. The decoder includes a common memory for storing the digital words provided by the prefix processor and a microcomputer capable of reading from and writing to the common memory. The microcomputer reads the data provided by the prefix processor, converts it to digital words representing the picture elements and stores the converted digital words in the common memory. The decoder includes a display processor which reads the converted digital words from the common memory to drive an image display device.

Claims

1. A decoder of teletext-like signals containing picture information for displaying by an imaging device, comprising:

a data processor responsive to said teletext-like signals for generating binary data therefrom;

a display processor for producing signals for said imaging device that contain said picture information;

a microcomputer responsive to said binary data for controlling operation of said display processor;

a memory for storing said binary data;

switching means for providing access to said memory for each of said data processor, display processor and microcomputer to transfer data therebetween, said switching means, when providing access to said memory for one of the data processor, display processor and microcomputer, exclusing the other two from access thereto; and

a timing unit for providing timing signals to control said switching means, said timing signals defining a recurring first access time slot wherein access to said memory is provided for said display processor, a recurring second access time slot wherein access to said memory is provided for said microcomputer and a recurring third access time slot wherein access to said memory is provided for said data processor, with the access time slots for said display processor being provided at predetermined time intervals.

2. A decoder as described in claim 1, wherein said data processor access time slot has a higher priority over said microcomputer access time slot when both are ready to transfer data to said memory.

3. A decoded of teletext-like signals containing picture information for displaying by an imaging device, comprising:

a data processor responsive to said teletext-like signals for generating binary data therefrom;

a display processor for producing signals for said imaging device that contain said picture information;

a microcomputer responsive to said binary data for controlling operation of said display processor;

a memory for storing said binary data;

switching means for providing access to said memory for each of said data processor, display processor and microcomputer to transfer data therebetween, said switching means, when providing access to said memory for one of the data processor, display processor and microcomputer, excluding the other two form access thereto; and

a timing unit for providing timing signals to control said switching means, said timing signals defining a sequence of access time slots to said memory that occur at regular intervals.

4. A decoder as recited in claim 3, further comprising a data storage register for receiving the data transferred from said memory, said register allowing said microcomputer to read said transferred data at a later time so that said switching means is free to perform a subsequent access to said memory after said data storage register receives said data transferred from said memory.

5. A decoder as recited in claim 3, wherein said switching means comprises a buss coupled to said memory and having a plurality of signal lines and a plurality of data drivers for driving said buss, said data drivers receiving at input ports thereof, respectively, address and data words from each of said microcomputer and data processor, and address words from said display processor for driving the corresponding address and data words on said buss at a particular time slot assigned to each of said data drivers, so that only one data driver is capable of driving said buss at any one time.

6. A decoder as recited in claim 3 wherein said data processor is given priority over said microcomputer for access to said memory in a time slot not otherwise assigned to said display processor.

7. A decoder as recited in claim 3 wherein said display processor is capable of reading a plurality of pixel data words each time said display processor is provided the access to said memory.

8. A decoder for teletext-like digital signals comprising:

a data processor receiving the teletext-like signals for extracting control and picture digital information therefrom;

a microcomputer for controlling the operation of the data processor;

a display processor for supplying picture information, that is derived from the picture digital information in such a way that the derived picture information is capable of being displayed in a display, each of said data processor, microcomputer and display processor, having a port for transferring a digital word thereon;

a memory having an address port, a data port for transferring data into and out of the memory and a plurality of memory locations;

first means having an input port for receiving said digital word that contains a memory address word, and having an output port for coupling the received memory address word that is received at said input port of said first means to the memory address port;

switching means for selectively transferring a digital word to the input port of the first means, the switching means being capable of selectively transferring a digital word from the microcomputer and from the data processor to a memory location, and a digital word from a memory location to the microcomputer and to the display processor, the memory location being determined by the memory address which is being provided by the output port of the first means at the time a transfer takes place, so that the data word transferred from the microprocessor or the data processor to a memory location while applying a certain memory address at any one time can be transferred at a later time to the microcomputer or to the display processor from the same memory location by applying the same certain memory address; and

a timing unit providing timing signals to control said switching means, said timing signals defining a sequence of access time slots to said memory that occur at regular intervals.