Timing synchronization circuit
First Claim
1. A timing synchronizing circuit, for every station in a communication system comprising a plurality of stations and one master station, said master station being a reference station for system synchronization in an asynchronous transmission system, comprising:
- an oscillator in every station for producing a clock signal of a frequency substantially equal to those of other stations;
a frequency divider in every station for frequency-dividing said clock signal, said frequency divider for each station defining frames and blocks within said frames, to format signal transmission between said stations;
detecting means for detecting signals of block units transmitted from the master station;
reset signal producing means for producing a reset signal, which defines a block start point of a block, from said signal being detected; and
timing setting means for initializing said frequency divider with the said of said reset signal.
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Accused Products
Abstract
A timing synchronization circuit for use in a multi-station communication system in which one station is a master station. The timing synchronization circuit within each station comprises a clock operating at a frequency nearly constant between the stations. The clock signal is frequency-divided to provide synchronization of the frames and blocks of the data being transmitted. The clock signal is reinitialized by a reset signal generated when a packet of data transmitted by the master station is received and recognized by the station by identifying code within the packet. The reinitialization accounts for the propagation delays relative to the master station.
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Citations
8 Claims
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1. A timing synchronizing circuit, for every station in a communication system comprising a plurality of stations and one master station, said master station being a reference station for system synchronization in an asynchronous transmission system, comprising:
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an oscillator in every station for producing a clock signal of a frequency substantially equal to those of other stations; a frequency divider in every station for frequency-dividing said clock signal, said frequency divider for each station defining frames and blocks within said frames, to format signal transmission between said stations; detecting means for detecting signals of block units transmitted from the master station; reset signal producing means for producing a reset signal, which defines a block start point of a block, from said signal being detected; and timing setting means for initializing said frequency divider with the said of said reset signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification