Synchronizing signal detecting circuit in a digital signal transmitting system

• US 4,596,981 A
• Filed: 05/29/1984
• Issued: 06/24/1986
• Est. Priority Date: 05/30/1983
• Status: Expired due to Term

• Current Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Original Assignee: Victor Company of Japan Limited (JVC Kenwood Corporation)
• Inventors: Ueno, Shoji, Nishikawa, Kazunori, Masuda, Isao, Komura, Makoto, Iwasaki, Yoshiki
• Primary Examiner(s): Weldon, Ulysses
• Assistant Examiner(s): Smith, Ralph
• Application Number:
  US06/615,237
• Time in Patent Office: 756 Days
• Field of Search: 340/825.2, 370/100, 370/108, 375/106, 375/113, 375/114, 375/116, 358/319, 328/63
• US Class Current: 375/368
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A synchronizing signal detecting circuit is used in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, where each of the blocks are made up of digital data which are information signals subjected to a digital modulation, a synchronizing signal having a fixed pattern, and an error checking code arranged at a location separated from a location of the synchronizing signal by a predetermined number of bits. The synchronizing signal detecting circuit comprises a counter which is reset when a synchronizing signal detection output which has been discriminated as being correct by use of the error checking code is continuously obtained for N times, where N is a natural number greater than or equal to two.

Claims

1. A synchronizing signal detecting circuit in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, each of said blocks being made up of digital data which are information signals subjected to a digital modulation, a synchronizing signal having a fixed pattern, and an error checking code arranged at a location separated from a location of said synchronizing signal by a predetermined number of bits, said synchronizing signal detecting circuit comprising:

a first detecting circuit supplied with said digital signal, for detecting a signal having the same fixed pattern as said synchronizing signal within the digital signal;

an error checking circuit for essentially detecting whether said synchronizing signal is correct by use of the error checking code within the digital signal at a point which is a transmitting duration of said predetermined number of bits after a point when a detection signal was produced from said first detecting circuit;

extracting means for extracting a clock signal from said digital signal;

a first counter for counting pulses in the clock signal which is extracted in said extracting means;

first decoder means for producing from a counted output of said first counter a signal having a period which is substantially equal to a period of a signal of one block;

counting means reset responsive to an output signal of said error checking circuit when said error checking circuit detects that said synchronizing signal is correct, for counting pulses in a signal which is obtained from an output signal of said first counter and has a period which is substantially equal to the period of the signal of one block;

delay means supplied with a counted output of said counting means, for producing a pulse signal which has been delayed by a predetermined delay time from a point when the counted output of said counting means becomes equal to M, where M is a natural number greater than or equal to 2;

resetting means for resetting said first counter responsive to the output detection signal of said first detecting circuit immediately after said delay means produces an output pulse signal or immediately after said first decoder produces an output signal;

a second detecting circuit for detecting that the output signals of said first detecting circuit and said first decoder means continuously coincide for N times for every period of the signal of one block in a state where the value of the counted output of said counting means is zero, where N is a natural number greater than or equal to 2;

a second counter reset responsive to the output detection signal of said first detecting circuit in a duration in which a detection signal is produced from said second detecting circuit, for counting pulses in said clock signal; and

second decoder means for decoding a counted output of said second counter, and for producing a synchronizing signal detection signal.

2. A synchronizing signal detecting circuit as claimed in claim 1 in which said first decoder means comprises a first decoder supplied with the counted output of said first counter, for producing a pulse signal which has a period substantially equal to the period of the signal of one block and is in phase with a last bit of said error checking code in said digital signal, and a second decoder supplied with the counted output of said first counter, for producing a pulse signal which has a period substantially equal to the period of the signal of one block and is in phase with a last bit of said synchronizing signal in said digital signal, said counting means counts the output pulse signal of said first decoder supplied thereto, and said resetting means and said second detecting circuit respectively receive the output pulse signal of said second decoder.

3. A synchronizing signal detecting circuit as claimed in claim 2 in which said resetting means comprises an OR circuit supplied with the outputs of said delay means and said second decoder, and a flip-flop having a reset terminal supplied with the output of said first detecting circuit and a set terminal supplied with an output of said OR circuit, and said flip-flop supplies a Q-output thereof to a reset terminal of said first counter.

4. A synchronizing signal detecting circuit as claimed in claim 1 which further comprises an AND circuit supplied with the output detection signal of said first detecting circuit and the output detection signal of said second detecting circuit, and an OR circuit supplied with outputs of said AND circuit and said second decoder means, for supplying an output signal thereof to a reset terminal of said second counter so as to reset said second counter.

5. A synchrnizing signal detecting circuit as claimed in claim 2 which further comprises an inverter supplied with a least significant bit of the output of said counting means, and an AND circuit supplied with outputs of said inverter and said second decoder, for supplying an output signal thereof to said second detecting circuit.