Transceiver for multi-drop local area networks

• US 4,597,082 A
• Filed: 03/06/1984
• Issued: 06/24/1986
• Est. Priority Date: 03/06/1984
• Status: Expired due to Fees

• Current Assignee: dbi Corp.
• Original Assignee: Controlonics Corporation
• Inventors: Hill, Lawrence W., Sarles, Frederick W.
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US06/586,863
• Time in Patent Office: 840 Days
• Field of Search: 375/75, 375/92, 375/8, 375/99, 375/104, 375/41, 329/105, 371/32, 371/33
• US Class Current: 714/748
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/5425 improving S/N by matching impedance, noise reduction, gain control
• CPC Class Codes: H04B 2203/5445 Local network
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 2203/5491 using filtering and bypassing
• CPC Class Codes: H04B 2203/5495 having measurements and testing channel
• CPC Class Codes: H04B 3/56 Circuits for coupling, blocking, or by-passing of signals
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling

Abstract

A multi-drop local area network utilizes alternating current power lines as a transmission channel. Identical transceivers are used as a master and as up to 255 slaves. Each transceiver comprises modulator and demodulator units and a microprocessor control unit which may be connected to a host. The modulator and demodulator are connected to the alternating current power line through a high pass filter comprising a split bobbin, iron core transformer having an air gap which also provides impedance matching. The demodulator includes a clipper and analog circuitry providing a band pass filter and generating a square wave corresponding to the received carrier. A state machine acting as a digital filter produces a received carrier signal only when each half cycle of the carrier square wave is of the proper duration and the carrier signal has existed for slightly more than one half of the transmitted bit duration, which is a predetermined number of carrier cycles.

The microprocessors are programmed to provide for block ahead acknowledgment, alternate transmissions between master and slaves; each block message comprises an acknowledgment non-acknowledgment bit, a message sequence bit, a polling sequence bit, and a longitudinal redundancy check. The carrier frequency utilized lies in the range of 20 to 40 KHz and preferably within the range between 27 and 33 KHz for a power line transmission channel. Error free 1200 Baud transmission rates are achieved in full duplex. Higher carrier frequencies and transmission rates are possible over less noisy transmission channels such as wire pairs.

Claims

1. A receiver for a local area network utilizing a digital carrier modulated transmission channel comprising:

A. means for detecting carrier and providing a square

B. a state machine for receiving said square wave said state machine being programmed to produce a binary output data signal that changes state only when said square wave has changed between existence and nonexistence for a predetermined time duration.

2. A receiver as defined in claim 1 wherein digital signals transmitted over said local area network exist for a predetermined number of carrier cycles;

and,

C. clock means for supplying to said state machine a clock signal at a multiple of the frequency of said carrier, and said state machine being responsive thereto to change its state.

3. A receiver as defined in claims 1 or 2 wherein said state machine sets its output data signal to one state upon determining the receipt of a first predetermined number of consecutive good square wave cycles and does not set its output data signal to the opposite state until determining that a second predetermined number of consecutive square wave cycles has not been received.

4. A transceiver for a local area network utilizing a digital carrier modulated transmission channel comprising:

A. a state machine for receiving a square wave corresponding to received carrier, said state machine being programmed to produce a binary output data signal that changes state only when said square wave has changed between existence and non existence for a predetermined time; and

B. a microprocessor connected to receive said data signal from said state machine, said microprocessor being connectable to a host device and, said microprocessor being programmed for a message format comprising;

1 bit for Ack or Nack;

1 bit for a message sequence number;

A data block; and

,

A logical redundancy check.