Assist circuit for a data bus in a data processing system

• US 4,598,216 A
• Filed: 08/27/1984
• Issued: 07/01/1986
• Est. Priority Date: 08/27/1984
• Status: Expired due to Term

• Current Assignee: Steinmetz Electrical LLC (Intellectual Ventures LLC)
• Original Assignee: NCR Corporation
• Inventors: Sani, Mehdi H., Lauffer, Donald K., Rostek, Paul M.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US06/644,407
• Time in Patent Office: 673 Days
• Field of Search: 307/200 B, 307/443, 307/453, 307/475, 307/480-481, 307/354-355, 307/546-548, 307/268, 307/269
• US Class Current: 326/17
• CPC Class Codes: H03K 19/01742 by means of a pull-up or down element

Abstract

A circuit for assisting transitions of a signal on a bus conductor having a sensing element connected to the bus conductor for determining if the bus conductor is in a first state or a second state, an assisting element for assisting transitions of a signal on the bus conductor between its first state and its second state responsive to electrical clock pulses, and a logic element connected to the sensing element and the assist element for enabling said assist element when the transmission of the mentioned signal is from its first state to its second state during said clock pulses, and for disabling the assisting element when the mentioned signal transition is from its second state to its first state during said clock pulses.

Claims

1. In a circuit for assisting transitions of a signal on a bus conductor, the improvement com- prising;

sensing means connected to the bus conductor for determining if said bus conductor is in a first state or a second state;

assist means for assisting transitions of a signal on said bus conductor between said first state and said second state responsive to electrical clock pulses; and

logic means connected to said sensing means and said assist means for enabling said assist means when said signal transition of said signal is from said first state to said second state during said clock pulses, and for disabling said assist means when said signal transition is from said second state to said first state during said clock pulses.

2. The circuit of claim 1 wherein said assist means comprises a current source, and a switch means for switching said current source onto said bus conductor when in a closed condition, and for breaking current flow from said current source to said bus conductor when in an open condition;

said switch means having a control input connected to said logic means for switching said switch means to its closed condition when said logic means enables said assist means, and for switching said switch means to its open condition when said logic means disables said assist means.

3. The circuit of claim 2 wherein said sensing means comprises a feedback conductor connected between said bus conductor and said logic means;

and

said logic means comprises a clock input for receiving said clock pulses, and a two state circuit having an output connected to the control input of said switch means, a first input connected to said clock input, and a second input connected to said feedback conductor;

said two-state circuit having a first enabling condition on its output when the bus conductor is at said first state at the start of a clock pulse on said clock input, and having a second disabling condition on its output when the bus conductor is at said second state at the start of a clock pulse on said clock input.

4. The circuit of claim 3 wherein said two-state circuit comprises:

an inverter having an input connected to the logic means end of said feedback conductor, and an output;

a first NOR gate having a first input connected to said clock input, a second input connected to the output of said inverter, and an output;

a second NOR gate having a first input connected to said clock input, a second input connected to the logic means end of said feedback conductor, and an output;

a set-reset type flip-flop having a reset input connected to the output of said first NOR gate, a set input connected to the output of said second NOR gate, and a Q output; and

an AND gate having a first input connected to said clock input, a second input connected to said Q output of said set-reset type flip-flop, and an output connected to the output of said two-state circuit.

5. The circuit of claims 1, 2, 3 or 4 wherein said logic means enables said assist means when the first state of said bus conductor is a low, and said logic means disables said assist means when the second state of said bus conductor is a high.