Barrier layer for photovoltaic devices

• US 4,598,306 A
• Filed: 07/28/1983
• Issued: 07/01/1986
• Est. Priority Date: 07/28/1983
• Status: Expired due to Term

• Current Assignee: United Solar Systems Corp.
• Original Assignee: Energy Conversion Devices
• Inventors: Nath, Prem, Izu, Masatsugu
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Mintel, William A.
• Application Number:
  US06/518,184
• Time in Patent Office: 1,069 Days
• Field of Search: 357/30, 357/30 B, 357/30 F, 357/30 J, 357/30 K, 357/2, 357/90, 357/58, 357/61, 357/16, 357/49, 357/54
• US Class Current: 257/458
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/076 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/208 Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

An improved semiconductor device, adapted to provide electrical current in response to light energy incident thereon, includes a first electrode, an active semiconductor body atop the first electrode, a second electrode atop the semiconductor body, and at least one defect region which is capable of providing a low resistance shunt path for the flow of electrical current between the electrodes of the device. The improvement comprises a continuous transparent barrier layer (1) operatively disposed between the semiconductor body and one of the electrodes of the device and (2) adapted to decrease the flow of electrical current through the at least one defect region of the semiconductor device. The barrier layer is formed from a material chosen from the group consisting essentially of oxides, nitride and carbides of: indium, tin, cadmium, zinc, antimony, silicon, chromium and mixtures thereof. Methods of (1) fabricating improved semiconductor devices and (2) preventing operational mode failures due to latent detents are also disclosed.

Claims

1. In a semiconductor device comprising a first electrode;

an active semiconductor body atop the first electrode, said semiconductor body including at least one triad of semiconductor layers, said triad comprised of two oppositely doped semiconductor layers having a layer of intrinsic semiconductor material disposed therebetween, said body adapted to provide for the flow of electrical current in response to the absorption of light energy incident thereon, a second electrode atop the semiconductor body; and

at least one defect region which is capable of providing a low resistance shunt path for the flow of electrical current between the electrodes;

the improvement comprising;

a continuous transparent barrier layer, formed of a material having an electrical resistivity greater than that of the electrodes, operatively disposed between the semiconductor body and one of the electrodes for decreasing the flow of electrical current through said at least one defect region of said semiconductor device.

2. A device as in claim 1, wherein the barrier layer is formed from a material chosen from the group consisting essentially of oxides, nitrides and carbides of:

indium, tin, cadmium, zinc, antimony, silicon, chromium and mixtures thereof.

3. A device as in claim 1, wherein the second electrode is transparent.

4. A device as in claim 3, wherein the barrier layer is operatively disposed between the semiconductor body and the second transparent electrode.

5. A device as in claim 4, wherein the transparent second electrode is formed of indium tin oxide and the barrier layer is formed of tin oxide.

6. A device as in claim 5, wherein the indium tin oxide is graded so as to form an upper conductive region predominantly of indium tin oxide and a lower, resistive, semiconductor body-contacting region predominantly of tin-oxide.

7. A device as in claim 4, wherein the semiconductor body comprises amorphous p-i-n layers and the first electrode is formed of a, highly conductive metal.

8. A device as in claim 7, wherein said barrier layer has a thickness of greater than 200 angstroms.

9. A device as in claim 3, wherein the first electrode is formed of stainless steel, and the barrier layer is operatively interposed between the stainless steel electrode and the semiconductor body.

10. A device as in claim 9, wherein the barrier layer is a material formed as a product of oxidation of the stainless steel electrode.

11. A device as in claim 10, wherein the barrier layer is a material formed as a product of nitridation of the stainless steel electrode.

12. A device as in claim 1, wherein the barrier layer is formed from a transparent Si based alloy having a resistivity of 10³ -10⁸ ohms-cm.

13. A device as in claim 12, wherein the Si based alloy is non-amorphous.

14. In a photovoltaic device comprising a substrate electrode;

an active semiconductor body atop the substrate electrode;

a transparent, electrically conductive electrode atop the semiconductor body; and

at least one defect region which is capable of providing a low resistance shunt path for the flow of electrical current between the electrodes;

said semiconductor body including at least one triad of semiconductor layers, said triad comprised of two oppositely doped semiconductor layers having a layer of intrinsic semiconductor material disposed therebetween and adapted to generate electrical current in response to the absorption of light incident thereon;

the improvement comprising;

a continuous transparent barrier layer, formed of a material having an electrical resistivity greater than that of the electrodes, operatively disposed between the semiconductor body and the transparent electrode for decreasing the flow of electrical current through said at least one defect region of said photovoltaic device.

15. A device as in claim 14, wherein said barrier layer is formed of a material chosen from the group consisting of oxides, nitrides and carbides of:

indium, tin, cadmium, zinc, antimony, silicon and mixtures thereof.

16. A device as in claim 14, wherein the barrier layer is formed of tin oxide and the transparent electrode is formed of indium tin oxide.

17. A device as in claim 14, wherein the transparent electrode is graded so as to form an upper, conductive electrode predominately of indium tin oxide and a lower, resistive predominately of tin oxide.

18. A device as in claim 17, wherein the barrier layer is formed from a transparent Si based alloy having a resistivity of 10³ -10⁸ ohm-cm.

19. A device as in claim 18, wherein the Si based alloy is non-amorphous.

20. A device as in claim 14, wherein the barrier layer is greater than 200 angstroms thick.