High power direct current switching circuit

• US 4,598,330 A
• Filed: 10/31/1984
• Issued: 07/01/1986
• Est. Priority Date: 10/31/1984
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Woodworth, George K.
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Wysocki, A. Jonathan
• Application Number:
  US06/666,587
• Time in Patent Office: 608 Days
• Field of Search: 361/2, 361/6, 361/13, 361/3, 361/8, 361/5, 361/9, 307/115, 307/134, 307/135
• US Class Current: 361/13
• CPC Class Codes: H01H 2009/545 comprising a parallel semiconductor switch being fired optically, e.g. using a photocoupler,
• CPC Class Codes: H01H 9/542 Contacts shunted by static switch means

Abstract

A DC power switching circuit connecting a load to a DC power source while suppressing arcing across a relay in the network. A normally open relay has its energizing coil connected to the control input of the circuit, the opposite end of the coil being connected to the gate of a silicon controlled rectifier. The SCR has its principal current conducting path connected between the load and the DC power source, for conducting current between the load and the power source during a first delay interval, thereby reducing the potential difference between the contacts of the relay so as to prevent its arcing during the closure of the contacts. An FET device has its principal current conducting path connected between the load and the DC power source and has its gate connected to a timer. The timer has a control input connected to the control input of the circuit so that it turns on the FET for a duration of a second delay interval in response to an off signal at the control input for the circuit so that the relay contacts are shunted while they are opening from a closed state, thereby preventing arcing across the contacts. In this manner, the relay is protected from arcing both on opening and closing of its contacts.

Claims

1. A DC power switching circuit, connecting a load to a DC power source, comprising:

a normally open relay, having an energizing coil with a first end connected to a control input terminal and a second end, and having a pair of switching contacts, the first contact of said pair being connected to said load and the second contact of said pair being connected to said DC power source, said contacts closing from an open state after a first delay interval in response to an on-signal at said control input terminal;

an SCR having its principal current conducting path connected between said load and said DC power source and having its control gate connected to said second end of said relay energizing coil, conducting current between said load and said power source during said first delay interval, thereby reducing the potential difference between said first and second contacts of said relay, preventing arcing between said relay contacts during the closure thereof;

an FET having its principal current conducting path connected between said load and said DC power source and having a control gate;

a timer having a control input connected to said control input terminal and an output connected to said gate of said FET, maintaining on said FET gate for a duration of a second delay interval in response to an off-signal at said control input terminal, said relay contacts opening from a closed state in response to said off-signal after a delay which is shorter in duration than said second delay interval;

said SCR gate turning off substantially when said off-signal occurs and said timer turning on said FET substantially when said off-signal occurs, said FET device in response thereto conducting current between said load and said power source during said second delay interval, thereby reducing the potential difference between said first and second contacts of said relay, for preventing arcing between said relay contacts during the opening thereof.

2. A DC power switching circuit, connecting a load to a DC power source, comprising:

a low voltage control section having a signal input for receiving an on/off signal;

a first voltage level detector in said low voltage section, preventing the operation of said circuit if said on/off signal has an insufficient voltage magnitude;

a high voltage switching section having a control input terminal connected to an output of said low voltage control section, switching high voltage DC power from said power source to said load in response to said on/off signal;

a second voltage level detector in said high voltage section, preventing the operation of said circuit if said DC power source has an insufficient voltage magnitude;

a normally open relay in said high voltage section, having an energizing coil with a first end connected to said control input terminal and a second end, and having a pair of switching contacts, the first contact of said pair being connected to said load and the second contact of said pair being connected to said DC power source, said contacts closing from an open state after a first delay interval in response to an on-signal at said control input terminal;

an SCR in said high voltage section having its principal current conducting path connected between said load and said DC power source and having its control gate connected to said second end of said relay energizing coil, conducting current between said load and said power source during said first delay interval, thereby reducing the potential difference between said first and second contacts of said relay, preventing arcing between said relay contacts during the closure thereof;

an FET in said high voltage section having its principal current conducting path connected between said load and said DC power source and having a control gate;

a timer in said high voltage section having a control input connected to said control input terminal and an output connected to said gate of said FET, turning on said FET gate for a duration of a second delay interval in response to an off-signal at said control input terminal, said relay contacts opening from a closed state in response to said off-signal after a delay which is shorter in duration than said second delay interval;

said SCR gate turning off substantially when said off-signal occurs and said timer turning on said FET substantially when said off-signal occurs, said FET device in response thereto conducting current between said load and said power source during said second delay interval, thereby reducing the potential difference between said first and second contacts of said relay, preventing arcing between said relay contacts during the opening thereof.