Microtelephone controller

• US 4,598,397 A
• Filed: 02/21/1984
• Issued: 07/01/1986
• Est. Priority Date: 02/21/1984
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: CXC Corporation
• Inventors: Godding, Patrick N., Nelson, Gary A.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Kuntz, Curtis
• Application Number:
  US06/582,069
• Time in Patent Office: 861 Days
• Field of Search: 370/60, 370/94, 370/58, 370/110.1, 370/84, 370/89
• US Class Current: 370/468
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04M 9/025 Time division multiplex systems, e.g. loop systems

Abstract

A large scale integrated circuit device is disclosed that can be used as a component in a variable bandwidth branch exchange system or for other applications utilizing programmable serial data rate conversion. The device can be a serial information interface between a system node and the voice and data channels in a telset or other similar data communications device. The device may be controlled and monitored by an external device such as a microprocessor, and can transfer control and status information between the external control device and the system node.

Claims

1. A switching device for transferring digital information between a system node which functions at a first rate and one or more devices which function at rates which are different than said first rate, the switching device comprising:

a system interface for communicating a signal stream including voice, data, and control information between the switching device and the system node and for providing signals identifying said voice, data, and control information in the switching device, the system interface including a system interface multiplexer operative to combine voice signals from an audio device and data signals from a data device in a message frame for transmission to the system node;

a microprocessor interface responsive to said identifying signals for communicating control information between a selected device and the switching device;

a voice interface responsive to said identifying signals for communicating voice information between an audio device and the switching device;

a data interface responsive to said signals for communicating data information between a data device and the switching device, with said local data device functioning at any of a plurality of rates; and

rate conversion logic for altering the rate of a selected portion of said information to a serial rate which corresponds to a data stream rate of one of said selected, audio, or data devices.

2. The device as recited in claim 1 wherein the rate conversion logic includes a gate circuit for extracting a data portion of a message frame received from the system node, the data portion corresponding to the signal portion to be communicated to the data device.

3. The device as recited in claim 2 further comprising synchronous and terminal rate logic operative to translate the data rate of the extracted data portion to the information rate of the data device, the synchronous and terminal rate logic including detection and counting circuitry operative to extract synchronization information from the signal portion.

4. The device as recited in claim 3 wherein the detection and counting circuitry further includes control circuitry operative to generate a clocking signal corresponding to the data rate of the extracted data portion.

5. The device as recited in claim 4 wherein the control circuitry includes a clock adjustment circuit operative to adjust the speed of the generated clock in response to fluctuations in the data rate of the extracted data portion of the message frame.

6. The device as recited in claim 3 wherein the rate logic further includes a buffer circuit for storing the extracted data portion of the signal stream, and a multiplexer circuit for gating the extracted data portion of the message frame to the data device at the clock rate of the data device.

7. The device as recited in claim 5 wherein the rate logic further includes a buffer circuit for storing the extracted data portion of the message frame, and a multiplexer circuit for gating the extracted data portion to the data device at the clock rate of the data device.

8. The device as recited in claim 1 wherein the system interface multiplexer is further operative to combine data with the voice and data signals in the message frame for communication to the system node.

9. The device as recited in claim 8 further comprising packet channel logic operative to communicate the control data portion of the message frame between the system node and the microprocessor interface.

10. The device as recited in claim 9 wherein the packet channel logic includes packet channel enable circuitry operative to form a communications path to the microprocessor interface during a portion of the signal stream dedicated to communication of control information.

11. The device as recited in claim 10 wherein the system interface further includes timing circuitry operative to generate said signal identifying said control information during the portion of the message frame from the system node dedicated to the communication of control information.

12. The device as recited in claim 1 wherein the system interface further includes timing circuitry operative to generate said signal identifying said voice information during those portions corresponding to communication of audio information.

13. The device as recited in claim 1 wherein the system interface further includes timing circuitry operative to generate said signal identifying said data information during those portions corresponding to communication of data information.

14. The device recited in claim 3 wherein the synchronous and terminal rate logic includes a data device interface and an encoding circuit, the encoding circuit being operative to structure data received from the data device in synchronous format.

15. The device as recited in claim 3 wherein the synchronous and terminal rate logic includes a data device interface for communicating data between the data device and the switching device.

16. The device as recited in claim 15 wherein the rate conversion logic further includes shift registers operative to adjust the data rate of data from the data device to conform to the data rate of the system node.

17. The device as recited in claim 15 wherein the data portion of the message frame transmitted to the system node includes a variable number of valid message bits, the number of message bits being determined by the data rate of the data device.

18. The device as recited in claim 15 wherein the data portion of the message frame received from the system node includes a variable number of valid data bits, the number of valid bits being determined in response to the data rate of the data device.

19. A switching device for transferring digital information between a system node which functions at a first rate and one or more devices which function at rates which are different than said first rate, the switching device comprising:

a system interface for communicating a signal stream including voice, data, and control information between the switching device and the system node, the system interface including a system interface multiplexer operative to combine voice signals from an external audio device, data signals from an external data device, and control information from an external microprocessor in a message frame for transmission to the system node, the system interface further including timing circuitry for receiving a message frame from the system node, the received message frame including voice, data, and control information, the timing circuitry being operative to generate separate enable signals in response to the occurrence of each of the voice, data, and control information portions of the received message frame;

a microprocessor interface responsive to said enable signals for communicating control information between the external microprocessor and the switching device;

a voice interface responsive to said enable signals for communicating voice information between the audio device and the switching device;

a data interface responsive to said enable signals for communicating data information between the external data device and the switching device, with said data device functioning at any of a plurality of rates; and

rate conversion logic for altering the rate of a selected portion of said message frame received from the system node to a serial rate which corresponds to a data stream rate of one of said microprocessor controller, audio device or data device.

20. A switching device for transferring digital information between a system node which functions at a first rate and one or more devices which function at rates which are different than said first rate, the switching device comprising:

means for communicating a signal stream comprising voice and data information between the switching device and system node;

means for providing signals identifying said voice and data information;

means respsonsive to said signals for communicating voice information between an audio device and the switching device;

means responsive to said signals for communicating data information between a data device and the switching device, with the data device functioning at any of a plurality of rates; and

means for altering the rate of a selected portion of said voice and data information to a serial rate which corresponds to a data stream rate of one of said audio device or data device.

21. A switching device as defined in claim 20 wherein the means for communicating includes means for combining voice signals from an audio device and data signals from a data device in a message frame for transmission to the system node.

22. A switching device as defined in claim 21 further comprising means for altering rates of the voice signals and the data signals from the devices to conform to a rate of the system node.