Method of making MOSFET by multiple implantations followed by a diffusion step

• US 4,599,118 A
• Filed: 09/24/1984
• Issued: 07/08/1986
• Est. Priority Date: 12/30/1981
• Status: Expired

• Current Assignee: Thomson Components-Mostek Corporation
• Original Assignee: Mostek Corporation (Rtx Corporation)
• Inventors: Chan, Tsiu C., Han, Yu-Pin
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/654,281
• Time in Patent Office: 652 Days
• Field of Search: 148/1.5, 148/187, 29/576 B, 29/571, 357/23 VD, 357/91
• US Class Current: 438/291
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 148/082 Ion implantation FETs/COMs

Abstract

A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V_T falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

Claims

1. A method for manufacturing a metal oxide semiconductor transistor device comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first insulating layer of silicon dioxide on an active surface of the substrate;

implanting ions of a first conductivity type into said substrate;

depositing a layer of polysilicon on said first insulating layer;

implanting ions of a second conductivity type through said polysilicon layer;

growing a second region of silicon dioxide, said silicon dioxide region being grown over said polysilicon layer;

placing a photoresistive mask over said second oxidation layer for forming a gate of the semiconductor device;

etching a predetermined portion of said second oxidation layer;

plasma etching said polysilicon layer;

removing a predetermined portion of said polysilicon layer underneath said second silicon dioxide layer;

etching said second layer of silicon dioxide;

stripping said photoresist area from said second oxidation layer;

implanting ions of the second conductivity type;

implanting ions of the first conductivity type;

etching said second layer of silicon dioxide overhanging said polysilicon gate layer;

etching said first layer of silicon dioxide surrounding said polysilicon gate layer;

implanting ions of said first conductivity type;

implanting ions of said second conductivity type;

diffusing the implanted ions into said substrate; and

oxidizing the active surface of said substrate, including said polysilicon gate.

2. The method of making a metal oxide semiconductor transistor device of claim 1, wherein the implantation of ions of the first conductivity type are boron ions and the implantation of ions of the second conductivity type are arsenic ions.