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Memory-programmable control

  • US 4,600,988 A
  • Filed: 09/13/1983
  • Issued: 07/15/1986
  • Est. Priority Date: 09/30/1982
  • Status: Expired due to Term
First Claim
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1. A memory-programmable controller for controlling the process cycle of a processing machine operating a process, the controller comprising a multiprocessor system having a master communications processor unit and a plurality of individual processor units, each processor unit including a coupling memory, each coupling memory coupling a respective processor unit to a common system bus, and further comprising input/output means coupled to said common system bus for transferring signals from the common system bus to and from the processing machine, said communications processor unit controlling the transfer of signals between the processor units and said processing machine, each processor unit further comprising subprogram memory means and data memory means which can be accessed directly by said communications processor unit, said communications processor unit comprising means for controlling the access of said processor units to the common system bus, said means for controlling comprising bus control unit means for providing access to the common system bus by only one of the processor units at a time, said bus control unit means comprising memory means having stored therein the access sequence of said processor units and the respective access duration times of the processor units to the common system bus, said access duration times comprising selectable integral multiples of a basic clock period, and further comprising means responsive to said stored access sequence and duration times for scanning a bus cycle, said bus cycle comprising a predetermined number of basic clock periods, and means for generating bus release signals, said bus release signals being coupled to respective ones of said processor units for providing access by said respective processor units to the common system bus during said bus cycle and further comprising means for monitoring the number of times the common system bus has been accessed by each processor unit within a predetermined number of bus release signals, said monitoring means comprising counter means for counting out respective predetermined periods of time for each of said processor units.

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