Image processor

• US 4,601,055 A
• Filed: 04/10/1984
• Issued: 07/15/1986
• Est. Priority Date: 04/10/1984
• Status: Expired due to Term

• Current Assignee: THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
• Original Assignee: THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
• Inventors: Kent, Ernest W.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Niessen, William G.
• Application Number:
  US06/598,602
• Time in Patent Office: 826 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/718, 364/724, 364/728, 364/514, 364/517, 382/41, 382/42, 382/49, 382/48, 358/166, 358/167
• US Class Current: 382/303
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06V 10/36 Applying a local operator, i.e. means to operate on image points situated in the vicinity of a given point; Non-linear local filtering operations, e.g. median filtering

Abstract

An iconic-to-iconic low-level image processor is provided which comprises alurality of identical sequential intermediate stages located between an input stage adapted to be connected to image sources such as analog or digital television cameras, ranging devices and conformal mapping arrays and an output stage adapted to be connected, e.g. to monitors, robot vision systems, iconic symbolic mapping devices and image processing computers. The intermediate stages are provided with forward pathway connections which afford sequential image processing as well as retrograde (feedback) pathway connections between adjacent stages in reverse sequence and within stage, recursive pathway connections for each stage. The stages each include neighborhood operators and image buffers and a number of operations are supported including neighborhood operations on images within each stage and between-stage operations on each pixel such as threshold, boolean and arithmetic operations, function mappings and the like.

Claims

1. An image pre-processor for low-level iconic-to-iconic image processing system, said processor comprising:

a plurality of sequentially arranged, multiply interconnected processor stages each including means for storing multiple complete images;

means providing a forward path connection between adjacent stages of said plurality of stages in sequence for transmitting complete processed images between those stages;

means providing backward path connections between adjacent stages of said plurality of stages in a reverse sequence to the forward path connections between the plurality of the stages for transmitting complete processed images between those stages; and

means providing a within stage recursive path connection for each stage of said plurality of stages wherein the output of the stage is connected back to an input to the stage for transmitting complete processed images between said output and said input of that stage.

2. An image processing system as claimed in claim 1 wherein each processor stage includes a pair of field buffers for holding a processed version of the image from a single field of data.

3. An image processing system as claimed in claim 2 wherein each processor stage includes means for enabling the carrying out of pointwise arithmetic and boolean operations, and neighborhood operations.

4. An image processing system as claimed in claim 1 further comprising at least one "wildcard" connection between the processor stages for enabling image frames to be moved between arbitrarily selected processor stages.

5. An image processing system as claimed in claim 4 wherein two of said "wildcard" connections are provided for each processor stage.

6. An image processing system as claimed in claim 1 wherein said processor stages each comprise identical modular image processing stages, and at least a portion of each modular stage is mounted on an interchangable circuit board.

7. An image processing system as claimed in claim 1 wherein each of said processor stages includes first and second parallel connected means for performing neighborhood operations, and said neighborhood operation performing means are selectively used as the source of forward path operations, backward path operations or forward and backward path operations for the associated processor stage.

8. An image processing system as claimed in claim 1 wherein each processor stage comprises means for performing neighborhood operations including arithmetic convolution operations.

9. An image processing system as claimed in claim 1 wherein each processor stage comprises means for performing neighborhood operations including a set of arbitrary boolean operations.

10. An image processing system as claimed in claim 1 wherein each of said processor stages includes means for performing region-of-interest operations.

11. An image processing system as claimed in claim 1 wherein each of said processor stages comprises a pair of buffers and further includes means for performing a table lookup function for producing an output from corresponding pixels from both of said buffers.

12. An image processing system as claimed in claim 1 wherein said each of said processor stages further includes a full-function arithmetic logic unit.

13. An image processor system as claimed in claim 1 wherein each processor stage provides transformation functions for application to each of the forward, backward and recursive path connections, and a combining function for application to the results of the transformation functions to provide a first input for that processor stage, each of said processor stages being connected to at least two "widcard" busses which enable images to be moved between arbitrarily selected stages, and which form second and third inputs to that processor stage, and each said processor stage further comprising a pair of image buffers adapted to be connected to said inputs;

means for enabling switching said first, second and third inputs between said image buffers, a pair of parallel connected means for performing neighborhood operations and adapted to be connected to the outputs of said buffers; and

means for enabling selective switching of the outputs of said buffers to said means for performing neighborhood operations, said processor stages further means for providing an arithmetic operator function and a look-up function, and further comprising switching means for enabling selection of the outputs of the means for performing neighborhood operations and the outputs of said image buffers as inputs for said function performing means, and further switching means for enabling selection, as the output of that stage, between the contents of the pair of image buffers, the outputs from the means for performing neighborhood operations, and the outputs of the means for performing arithmetic operator and table lookup functions for selective routing thereof to a pair of "widcard" output busses and forward, backward and recursive path connection outputs.

14. An image processor as claimed in claim 1 said processor stages further comprise means for performing a plurality of different image processing operations which are selected based on data stored by the image storing means associated with that stage.

15. An image processor as claimed in claim 1 wherein at least one of said path connection providing means each includes means for transforming the resolution level of the image transmitted over that path connection.