Pixel non-uniformity correction system

• US 4,602,291 A
• Filed: 05/09/1984
• Issued: 07/22/1986
• Est. Priority Date: 05/09/1984
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Temes, Gabor C.
• Primary Examiner(s): Rubinson, Gene Z.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/608,594
• Time in Patent Office: 804 Days
• Field of Search: 358/213, 358/221, 358/241
• US Class Current: 348/243
• CPC Class Codes: H04N 1/401 Compensating positionally unequal response of the pick-up or reproducing head H04N1/403 takes precedence
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction

Abstract

A solid state imager wherein a pixel non-uniformity correction system compensates for photosite non-uniformities by providing a linear correction method and utilizing three modes: mode #1--dark current detection, mode #2--uniform illumination, and mode #3--data detection mode. In the first calibration cycle, the outputs of all the photocells on an imager 10, representing "dark current" are stored in an "offset" memory 14. In the second calibration cycle, a uniform illumination from a constant light level is applied to the imager 10. This uniform illumination signal is passed to an arithmetic unit 18 where the dark current signal is subtracted from it and the difference is then stored in gain memory 28. The gain memory passes this signal back to the arithmetic unit 18, so that in the third mode, the data detection mode, the arithmetic unit 18 can electronically correct the data signals that were non-uniformly affected by the internal characteristics of the imager.

Claims

1. A pixel non-uniformity correction system for use in an imager (10) wherein said system operates in three separate modes, the improvement comprising:

offset memory means (14) coupled to said imager for storing the dark current signal from said imager in a first mode when no light is directed to said imager,

arithmetic unit means (18) coupled to said imager and said offset memory means for storing the signal from said imager in a second mode when a light of uniform, predetermined level is directed to said imager, said arithmetic unit means also subtracting the dark current signal received from said offset memory means from the signal generated upon application of said uniform light thereby generating a difference signal,

gain memory means (28) coupled to said arithmetic unit means for receiving and storing said difference signal, said gain memory means also coupled back to said arithmetic unit means for presenting said difference signal to said arithmetic unit means when the system is placed in a third, operating mode,

first switch means (SW2) for switching the output from said arithmetic unit means from said gain memory means to the system output such that said arithmetic unit means now compensates actual data signal from said imager upon data modulated light directed thereto for non-uniformities in each photosite of said imagers, and

second switch means (SW1) for coupling said imager to the offset memory means in the first mode and to the arithmetic unit means in the second and third modes.

2. A system for correcting pixel non-uniformities in a solid state imager, where said imager response can be approximated by the linear relation

3. An arithmetic circuit comprising:

a first plurality of capacitor means (C1-Cm), the second terminals of capacitor means being directly connected together, a first plurality of switch means (B0-Bn) for selectively coupling the first terminals of said first plurality of capacitor means to a reference voltage, said first plurality of switch means being selectively responsive to first binary signals B being applied thereto,

a second capacitor means (CO), the second terminal of which being directly connected to the second terminals of said first plurality of capacitor means, a second switch means (.0.2) for coupling said second capacitor means, via the first terminal thereof, to an input applied signal source Y2 or Y, such that said charge transferred through said first plurality of capacitor means is subtracted from the charge transferred by said second capacitor means,

a third plurality of capacitor means (C10-Cx) connected together, the first terminals of said third plurality of capacitor means being directly connected together and to the second terminals of said first plurality of capacitor means and said second capacitor means, a third plurality of switch means for selectively coupling the second terminals of said third plurality of capacitor means to a common point, said third plurality of switch means being selectively responsive to second binary signals M being applied thereto, and

operational amplifier means (60) having first and second inputs and one input, said first input being connected to the second terminals of said first plurality of capacitor means and said second capacitor means and said first terminals of said capacitor means, said second input being grounded, and said output being connected to said common point of said third plurality of capacitor means, such that signal B is subtracted from signal Y2 (or Y), the resultant signal Y2-B (or Y-B) being divided by signal M, thus affecting the resultant gain of said operational amplifier.

4. The arithmetic circuit as set forth in claim 3 further including a fourth plurality of switch means (.0.1) for connecting the first terminals of said first plurality of capacitor means and said second capacitor means and the second terminals of said third plurality of capacitor means to ground potential and to short circuit the output and inverting input of operational amplifier means (60).

5. The arithmetic circuit as set forth in claim 4 wherein said first plurality of capacitor means and said second plurality of capacitor means each includes capacitors, the values of which increase with the powers of two.

6. The arithmetic circuit as set forth in claim 5 further including a fifth plurality of switch means (.0.2) for connecting said first and third pluralities of capacitor means and said second capacitor means to said reference voltage upon the selective actuation of said first plurality of switch means.

7. The arithmetic circuit as set forth in claim 6 further including a sixth switch means (SW3) in the return of said second terminals of said third plurality of capacitor means to selectively isolate said third plurality of capacitor means.