Module construction for semiconductor chip

• US 4,603,345 A
• Filed: 03/19/1984
• Issued: 07/29/1986
• Est. Priority Date: 03/19/1984
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Trilogy Computer Development Partners, Ltd.
• Inventors: Sliwa, John W., Amdahl, Carlton G., Amdahl, Gene M., Lee, James C. K., Kucharek, Andrzej, Matouk, Anthony, Beall, Robert J.
• Primary Examiner(s): Davie, James W.
• Assistant Examiner(s): Economou, Vangelis
• Application Number:
  US06/590,651
• Time in Patent Office: 862 Days
• Field of Search: 165/80 B, 165/80 C, 357/82, 357/81, 357/79, 361/385, 361/386, 361/387, 361/407
• US Class Current: 257/691
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A module for a semiconductor chip is disclosed. The module includes a heat sink with a flat surface to which the back face of the semiconductor chip is directly bonded. The exposed face of the chip has an array of power, ground and signal contacts. A plurality of alternating power and ground bus bars span the exposed face of the chip. A multilayer ceramic is located on the other side of the bus bar array and has a surface proximate the power and ground bus bars with an array of contacts which correspond to at least the signal contacts on the chip. Power leads connect the power bus bars to adjacent power contacts on the chip; ground leads connect the ground bus bars to adjacent ground contacts on the chip; and signal leads pass between adjacent power and ground bus bars and interconnect the signal contacts on the chip with the corresponding signal contacts on the ceramic. A plurality of connectors emanate from the ceramic and are electrically coupled by vias or traces through the ceramic to the signal contacts for the transmission of signals to and from the chip.

Claims

1. A semiconductor chip module comprising:

a heat sink;

a semiconductor chip with electronic circuits formed therein having one face attached to the heat sink and having power, ground and signal contacts on the opposite, exposed face;

a conductor board disposed parallel to and spaced-apart from the exposed face of the chip, said connector board having a plurality of contacts arranged in a pattern corresponding to the contacts on the chip;

a power bus intermediate the semiconductor chip and the conducutor board, said power bus spanning the exposed face of the chip and having interstitial gaps;

a ground bus intermediate the semiconductor chip and the conductor board and electrically isolated from the power bus, said ground bus spanning the exposed face of the chip and having interstitial gaps;

power leads connecting the power bus to the power contacts on the chip;

ground leads connecting the ground bus to the ground contacts on the chip;

signal leads passing through the gaps in the power and ground buses and electrically isolated therefrom, said signal leads interconnecting the signal contacts on the semiconductor chip with the corresponding signal contacts on the conductor board; and

a plurality of connectors emanating from the conductor board and electrically coupled through the board to the signal contacts on the board for the transmission of signals to and from the chip.

2. The module of claim 1 wherein the heat sink has a flat surface, and the chip is attached flush to the flat surface of the heat sink.

3. The module of claim 2 wherein the heat sink comprises a fluid cavity proximate said flat surface, and an inlet and an outlet to said cavity to flow a cooling fluid.

4. The module of claim 3 wherein the fluid cavity includes a planar array of aligned heat conductive fins in heat transfer communication with the flat surface, and tortuous inlet and outlet paths from the inlet and the outlet to the respective ends of the fin array to equalize pressure in the fluid and promote equal fluid flow between the various fins.

5. The module of claim 3 wherein the cooling fluid is a liquid.

6. The module of claim 3 wherein the cooling fluid is water.

7. The module of claim 1 wherein only one semiconductor chip is attached to the heat sink.

8. The module of claim 1 wherein the heat sink is constructed of molybdenum.

9. The module of claim 1 wherein the heat sink is electrically coupled to a power terminal and to the power bus to define a power connection to the chip.

10. The module of claim 1 wherein the plurality of contacts on the conductor board are a mirror image of at least the signal contacts on the exposed face of the chip.

11. The module of claim 10 wherein the plurality of contacts on the conductor board are a mirror image of the power, ground and signal contacts on the exposed face of the chip.

12. The module of claim 1 wherein the power bus comprises a plurality of parallel power bus bars separated by gaps and the ground bus comprises a plurality of parallel ground bus bars disposed between at least some of the gaps between adjacent power bus bars.

13. The module of claim 12 and additionally comprising a power bus bar frame and a ground bus bar frame, the respective power and ground bus bars being mounted to said frames and electrically coupled thereto.

14. The module of claim 13 wherein the power bus bar frame is electrically coupled to the heat sink and the ground bus bar frame is electrically coupled to a conducting plate which is mounted on but electrically isolated from the heat sink.

15. The module of claim 1 wherein the semiconductor chip has an area of about 3,600 square millimeters.

16. The module of claim 1 wherein the conductor board is a multilayer ceramic.

17. The module of claim 1 wherein the connectors are pins.

28. The module of claim 1 or 18, wherein the chip is a single, unitary chip having an area of about 3,600 square millimeters.

18. A semiconductor chip module comprising:

a heat sink constructed of thermally and electrically conductive material having an internal cavity and a flat surface cooled by circulation of a cooling fluid through the cavity;

means for applying a preselected voltage to the heat sink;

a semiconductor chip with electronic circuits formed therein having one face flush with the cooled surface of the heat sink and having power, ground and signal contacts on the opposite, exposed face;

power distribution means including an electrically conductive frame electrically coupled to the heat sink and power bus bars mounted on the frame and spanning the exposed face of the chip;

ground means including a ground frame proximate the power frame but electrically isolated therefrom and ground bus bars mounted on the frame and spanning the exposed face of the chip;

means for electrically coupling the power bus bars and the ground bus bars to the respective power and ground contacts on the chip;

a conductor board having a surface proximate the power and ground bus means opposite from the chip, said surface having a plurality of contacts which correspond to at least the signal contacts on the chip; and

a plurality of individual connectors passing through the power distribution means and ground means for electrically coupling the signal contacts on the chip with the signal contacts on the conductor board.

19. The module of claim 18 wherein the preselected voltage is a negative voltage.

20. The module of claim 19 wherein the preselected voltage is -5 volts.

21. The module of claim 18 wherein the thermally and electrically conductive material is molybdenum.

22. The module of claim 18 wherein the power and ground bus bars are interleaved.

31. The module of claim 18 wherein the chip is soldered to the heat sink.

23. A semiconductor chip module comprising:

a heat sink;

a semiconductor chip with electronic circuits formed therein having one face flush with the heat sink and having power, ground and signal contacts on the other, exposed face;

a conductor board having a surface juxtaposed to and spaced from the exposed face of the semiconductor chip, said juxtaposed surface having a plurality of contacts which correspond to at least the signal contacts of the chip;

means for providing a circumferential hermetic seal between the semiconductor chip and the conductor board to define an enclosed chamber therebetween;

power and ground bus means within the chamber and spanning the exposed face of the chip and having interstitial gaps, said power and ground bus means being isolated from the semiconductor chip by a first resilient insulating layer and from the conductor board by a second resilient insulating layer, said resilient layers allowing fro differential thermal expansion between the chip, bus means, and the conductor board;

power and ground leads connecting the power and ground bus means respectively to the power and ground contacts on the chip; and

signal leads passing through the gaps in the bus means and interconnecting the signal contacts on the chip with the corresponding signal contacts on the conductor board with one end of each signal lead disposed between the chip contact and the first resilient insulating layer so that the first resilient layer biases the lead against the chip contact and the other end of each signal lead disposed between the conductor board contact and the second resilient layer so that the second resilient layer biases the lead against the conductor contact.

24. The module of claim 23 wherein the power and ground bus means include a plurality of power and ground bus bars, and wherein fhe hermetic sealing means includes power and bus bar frames respectively supporting the power and ground bus bars.

25. The module of claim 24 wherein the power bus bar frame is sealed to the heat sink, and the ground bus bar frame is sealed to the power bus frame and to the conductor board.

26. The module of claim 25 wherein the conductor board includes a frame, the ground bus bar frame being sealed to the conductor board frame.

27. The module of claim 23 wherein the conductor board is a ceramic having internal traces from each contact to respective pins on the side of the ceramic opposite from the contacts.

29. The module of claim 24 wherein the heat sink is liquid cooled.

30. The module or claim 29 in which the liquid is water.

32. An improved semiconductor chip module of the type wherein a semiconductor chip is mounted with one face disposed against a heat sink and another face disposed toward a conductor board, wherein the other face of the semiconductor chip includes a plurality of signal contacts arranged in a preselected pattern and said conductor board includes a plurality of signal contacts arranged in an at least partially corresponding pattern so that connection between the contacts on the chip and those on the conductor board is facilitated, the improvement comprising:

at least one layer intermediate the chip and the conductor board having a plurality of resilient bumps arranged in a pattern corresponding at least partially to that of signal contacts on the chip; and

a plurality of flexible leads penetrating one layer adjacent the resilient bumps and connecting the contacts on the chip with those on the conductor board, wherein the flexible leads are biased against the contacts on the chip by said bumps.

33. An improved semiconductor chip module as in claim 32, further comprising a second layer intermediate the chip and the connector board having a plurality of resilient bumps arranged thereon so that the flexible leads penetrate the second layer and are biased against the contacts on the conductor board by said bumps on the second layer.

34. An improved semiconductor module as in claim 33, further comprising power and ground bus means isolated between said first and second layers intermediate the chip and the conductor board, wherein some of the flexible leads are electrically connected to the power and bus means.

35. An improved semiconductor chip module as in claim 34, wherein said power and ground bus means comprises a plurality of interleaved power and ground bus bars electrically isolated from one another.