Method for composing addresses of a memory

• US 4,603,348 A
• Filed: 01/24/1983
• Issued: 07/29/1986
• Est. Priority Date: 01/27/1982
• Status: Expired due to Fees

• Current Assignee: Dainippon Screen Graphics (USA) LLC (SCREEN Holdings Co., Ltd.)
• Original Assignee: Dainippon Screen Graphics (USA) LLC (SCREEN Holdings Co., Ltd.)
• Inventors: Inoue, Toshifumi, Yamada, Mitsuhiko, Nishida, Tsukasa
• Primary Examiner(s): Groody, James J.
• Application Number:
  US06/460,286
• Time in Patent Office: 1,282 Days
• Field of Search: 358/75, 382/56, 382/44, 365/189
• US Class Current: 358/500
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A method for subdividing the addresses of a multi-dimensional memory, having n-dimensional addresses defined over a logical address space which is divided into a plurality of unit divisions. Each unit division has several vertices each of which is addressable by one of the n-dimensional addresses. Each one of the addresses associated with a given unit division is divided and allocated to a distinct memory bank so that no two addresses of the same unit division are in the same memory bank. There are a total of 2ⁿ memory banks, each having independent data lines and address lines. The original n-dimensional address of the vertices determines to which memory bank the vertex address will be allocated. Moreover, the n-dimensional address also determines the address of the given vertex within the memory bank to which it has been allocated. Thus, the data corresponding to all the vertices of a given unit division can be accessed simultaneously to thereby significantly reduce data retrieval times in many applications.

Claims

1. A method for subdividing the memory locations of an n-dimensional memory into distinct groups and allocating each group to a respective memory bank, wherein said n-dimensional memory includes defined therein a plurality of unit divisions, each unit division having a plurality of vertices, each one of said vertices being identified by a unique n-dimensional address, said method comprising the steps of:

providing 2ⁿ of said respective memory banks wherein said n equals the number of dimensions associated with said n-dimensional memory, each one of said memory banks being identified by a unique identifying number; and

deriving from each said n-dimensional address a value which corresponds to said identifying number, said value indicating to which said respective memory bank said n-dimensional address is to be allocated, said value being mathematically derived from said n-dimensional address such that no two n-dimensional addresses associated with a given one of said unit divisions are allocated to a single memory bank.

2. The method of claim 1, wherein said unique identifying number of said memory banks is an integer selected from the series of integers 0, 1, 2, 3 . . . 2ⁿ -1 and in which each of said n-dimensional addresses is represented as one of the series A₁, A₂, . . . , A_n and in which said value for each n-dimensional address equals the residue which is obtained by dividing ##EQU8## by 2ⁿ, wherein k is an integral counter than runs from 1 to n for performing said summation.

3. The method of claim 2, in which each n-dimensional address which is allocated to a given memory bank is reassigned a new n-dimensional address, the new n-dimensional address being derived from the relationship ##EQU9## in which only the integer result of the calculation is used for the new n-dimensional address and the fractional part is discarded.

4. The method of claim 1, in which the steps are applied to convert a first set of color signals C, M, Y and K which correspond to cyan, magenta, yellow and black color inks to a second set of color signals R, G and B corresponding to red, green and blue colors which are employed in a color display system, said method including the steps of providing 2⁴ of said memory banks, each one of said memory banks having independent data lines and address lines, each one of said memory banks being identified by a unique one of the series of numbers, 0, 1, 2, 3, . . . and 15, each n-dimensional address being represented as (C, M, Y, K) corresponding respectively to said cyan, magenta, yellow and black signals, each one of said n-dimensional addresses being allocated to a respective memory bank whose identifying number equals the residue of the equation C+2M+4Y+8K/2⁴.

5. The method of claim 1, in which each of said memory banks comprises independent data lines and address lines.

6. The method of claim 2, in which each of said memory banks comprises independent data lines and address lines.

7. The method of claim 3, in which each of said memory banks comprises independent data lines and address lines.

8. The method of claim 1, wherein said unique identifying number of said memory banks is an integer selected from the series of integers 0, 1, 2, 3, . . . 2ⁿ -1 and wherein each of said n-dimensional addresses is represented as one of the series A₁, A₂, . . . , A_n and wherein said value for each n-dimensional address equals the residue which is obtained by dividing the quantity

9. A memory based, multi-dimensional, interpolation apparatus for providing, simultaneously, a set of data associated with and derived from an n-dimensional data base which includes a plurality of unit divisions, each unit division having a plurality of vertices, each of said vertices being identified by an n-dimensional address, said apparatus comprising:

2ⁿ memory banks, n being equal to the dimension of the interpolation apparatus;

means for mathematically deriving from each n-dimensional address a value, said value determining in which one of said memory banks a data item corresponding to said n-dimensional address is to be stored, said data item being stored in a memory bank in which another data item associated with said set of data is not stored; and

means for generating addresses for each one of said memory banks to thereby enable simultaneous retrieval of said set of data from said memory banks.

10. A method for subdividing the memory locations of an n-dimensional memory into distinct groups and allocating each group to a respective memory bank to provide simultaneous access to sets of data stored in said memory locations, comprising the steps of:

defining in the memory locations of said n-dimensional memory a plurality of unit divisions, each unit division to contain one such set of data to be accessed, and each unit division having a plurality of vertices for containing the respective data constituting such set of data, and each one of said vertices being identified by a unique n-dimensional address,

subdividing the memory locations of said memory into 2ⁿ respective memory banks, wherein n equals the number of dimensions associated with said n-dimensional memory, each one of said memory banks being identified by a unique identifying number; and

deriving from each said n-dimensional address a value which corresponds to one of said identifying numbers, said value indicating to which said respective memory bank said n-dimensional address is to be allocated, said value being mathematically derived from said n-dimensional address such that no two n-dimensional addresses associated with a given one of said unit divisions are allocated to a single memory bank.

11. The method of claim 10, wherein said unique identifying number of said memory banks is an integer selected from the series of integers 0, 1, 2, 3, . . . 2ⁿ -1 and in which each of said n-dimensional addresses is represented as one of the series A₁, A₂, . . . , A_n and in which said value for each n-dimensional address equals the residue which is obtained by dividing the quantity

12. The method of claim 11, in which each n-dimensional address which is allocated to a given memory bank is reassigned a new n-dimensional address, the new n-dimensional address being derived from the relationship ##EQU10## in which only the integer result of the calculation is used for the new n-dimensional address and the fractional part is discarded.

13. The method of claim 10, in which each of said memory banks comprises independent data lines and address lines.

14. The method of claim 11, in which each of said memory banks comprises independent data lines and address lines.

15. The method of claim 12, in which each of said memory banks comprises independent data lines and address lines.