Mailing system interface interprocessor communications channel

• US 4,603,400 A
• Filed: 09/30/1982
• Issued: 07/29/1986
• Est. Priority Date: 09/30/1982
• Status: Expired due to Term

• Current Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Original Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Inventors: Daniels, Edward P.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Jaser, Samir
• Application Number:
  US06/430,091
• Time in Patent Office: 1,398 Days
• Field of Search: 364/200, 364/900
• US Class Current: 710/72
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G07B 17/00193 Constructional details of apparatus in a franking system
• CPC Class Codes: G07B 17/00314 Communication within apparatus, personal computer [PC] system, or server, e.g. between printhead and central unit in a franking machine
• CPC Class Codes: G07B 17/00733 Cryptography or similar special procedures in a franking system
• CPC Class Codes: G07B 2017/00258 Electronic hardware aspects, e.g. type of circuits used
• CPC Class Codes: G07B 2017/00322 Communication between components/modules/parts, e.g. printer, printhead, keyboard, conveyor or central unit

Abstract

In a mailing system including a postage value determining system processor which communicates along parallel channels and peripheral subsystem processors adapted to communicate with a system processor along a serial data bus, an interface is provided between the system processor and the serial bus. The interface includes a first and a second communications processor. The first processor is programmed to communicate with the system processor and with the second communications processor. The second communications processor is programmed to communicate with the first processor and with peripheral subsystem processors through the serial bus. Data and control signals are transmitted between the communications processors through an interprocessor channel. The interprocessor channel includes lines connected to reference voltage levels for providing appropriate signal levels for recognition by the communications processors which operate on different voltage signal levels.

Claims

1. An interprocessor channel operatively interconnecting a first digital system and a second digital system, said first digital system having data input lines paired with data output lines respectively providing and responding to first and second voltages for transmitting and receiving digital signals, and said second digital system having bi-directional data lines responsive to third and fourth voltages for receiving digital signals and providing said third voltage and a floating output state for transmitting digital signals, said channel comprising:

(a) a first reference source for providing a first reference voltage substantially equal to said third voltage;

(b) a second reference source for providing a second reference voltage substantially equal to said fourth voltage;

(c) a plurality of switch means, each responsive to digital signals on a preselected one of said data output lines for connecting and disconnecting said first reference source to a preselected one of said bi-directional lines;

(d) a plurality of current limiting resistors each connecting one of said preselected bi-directional lines to said second reference source;

(e) a plurality of buffers responsive to said third and fourth voltages for receiving digital signals and providing said first and second voltages to retransmit said digital signals, said buffers connecting said preselected bi-directional lines to preselected data input lines;

(f) said first digital system controlling said switch means to disconnect said first reference source from said bi-directional lines when said second digital system is transmitting, whereby data may be transmitted from said bi-directional lines through said buffers to said data input lines; and

,

(g) said second digital system providing a floating output state on said bi-directional lines when said first digital system is transmitting, whereby said data output lines control said switch means to switch said bi-directional lines between said third and fourth voltages.

2. A channel as described in claim 1 further comprising dedicated lines for transmitting digital signals between said digital systems to establish appropriate transmitting and receiving states in said digital systems.

3. A channel as described in claim 1 wherein said first and third voltages are substantially equal.

4. A channel as described in claim 2 wherein said first and third voltages are substantially equal.

5. A channel as described in claim 3 wherein said switch means comprise transistors connected between said first reference source and said bi-directional lines, the basis of said transistors being operatively connected to said output lines.

6. A channel as described in claim 1 wherein said first and second voltages are compatible with TTL logic and said fourth voltage is substantially negative.

7. A channel as described in claim 3 wherein said first and second voltages are compatible with TTL logic and said fourth voltage is substantially negative.

8. A channel as described in claim 4 wherein said first and second voltages are compatible with TTL logic and said fourth voltage is substantially negative.

9. A channel as described in claim 5 wherein said first and second voltages are compatible with TTL logic and said fourth voltage is substantially negative.