Operation mode setting system for a microprocessor
First Claim
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1. An operation mode setting system for a microprocessor operable in a plurality of operation modes, said operation mode setting system comprising in a single integrated circuit:
- a microprocessor having a plurality of operation modes;
a reset input terminal connected to said microprocessor for receiving a reset signal;
a mode input terminal for receiving an analog voltage the amplitude of which determines exclusively a corresponding one of said plurality of operation modes;
an analog-to-digital converter means connected to said mode input terminal for converting said analog voltage to a digital signal representative of the amplitude thereof;
a decoder means connected to said analog-to-digital converter means for decoding said digital signal and connected to said microprocessor for generating a signal for setting said microprocessor at said one of said plurality of operation modes corresponding solely to the amplitude of said analog voltage; and
means responsive to a reset signal applied to said reset input terminal for applying said decoded signal to said microprocessor to set the operation mode thereof when a reset signal is applied.
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Abstract
An operation mode setting system is provided in a microprocessor operable in a plurality of operation modes. The operation mode setting system has a signal input line through which an analog voltage corresponding to any of the respective operation modes is applied to an analog-to-digital converter circuit which is built in the microprocessor. The output signal from the analog-to-digital converter circuit is decoded by a decoder, and the microprocessor is set at the predetermined operation mode in response to the decoded output signal.
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Citations
6 Claims
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1. An operation mode setting system for a microprocessor operable in a plurality of operation modes, said operation mode setting system comprising in a single integrated circuit:
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a microprocessor having a plurality of operation modes; a reset input terminal connected to said microprocessor for receiving a reset signal; a mode input terminal for receiving an analog voltage the amplitude of which determines exclusively a corresponding one of said plurality of operation modes; an analog-to-digital converter means connected to said mode input terminal for converting said analog voltage to a digital signal representative of the amplitude thereof; a decoder means connected to said analog-to-digital converter means for decoding said digital signal and connected to said microprocessor for generating a signal for setting said microprocessor at said one of said plurality of operation modes corresponding solely to the amplitude of said analog voltage; and means responsive to a reset signal applied to said reset input terminal for applying said decoded signal to said microprocessor to set the operation mode thereof when a reset signal is applied. - View Dependent Claims (2, 3, 4, 6)
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5. An operating mode setting system for a microprocessor consisting of an integrated circuit on a single semiconductor substrate comprising:
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a microprocessor having a plurality of operation modes greater than three; an operation mode decoder connected to said microprocessor and responsive to a digital signal for setting a microprocessor mode of operation; a digitizing circuit for producing a binary digital output signal representative of the amplitude of an applied analog input signal;
said digital output signal being applied to said operation mode decoder as the digital input signal thereto;a single mode input terminal for receiving said analog input signal, said mode input terminal being connected to said digitizing circuit to provide the analog input signal thereto; a reset input terminal connected to said microprocessor for receiving a reset signal; and means responsive to a reset signal applied to said reset input terminal to cause said digital output signal to be applied to said operation mode decoder to set an operation mode of said microprocessor in accordance with the amplitude of an applied analog input signal at the time of said reset signal.
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Specification