System for detecting and recovering a transmitted signal

• US 4,606,050 A
• Filed: 07/22/1983
• Issued: 08/12/1986
• Est. Priority Date: 07/30/1982
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha 72 Horikawa-Cho Saiwai-Ku Kawasaki-Shi Japan
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Marui, Kuniyoshi, Sekigawa, Tatsuaki, Honda, Naoto, Gotoh, Akio, Tsutsumi, Syuitsu
• Primary Examiner(s): ORSINO JR, JOSEPH
• Application Number:
  US06/516,359
• Time in Patent Office: 1,117 Days
• Field of Search: 375/75, 375/80, 375/82, 375/94, 375/95, 375/23, 329/104, 329/107
• US Class Current: 375/316
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection

Abstract

What is disclosed is a system for recovering encoded data from a transmitted signal. A clock regenerating circuit regenerates a clock signal from the data bits encoded in the signal. The regenerated clock signal is used to synchronize an up/down with each individual data bit. When a data bit is at a logic "H", the counter counts from a predetermined value in an upward direction and when the data bit is at a logic "L", the counter counts in a downward direction from a predetermined value. The count after each bit-time is used to provide a signal representative of the logic state of that data bit. Accordingly, a reproduced data signal can be accurately obtained.

Claims

1. A system for detecting and recovering the information encoded in a data signal having NRZ start codes and SPL information codes, wherein said NRZ start codes and said SPL information codes include a plurality of information bits, a portion of each of said bits having a determinable signal power, said system comprising:

start code detecting means for detecting the ends of said NRZ start codes and providing start code signals accordingly;

clock signal regenerating means responsive to said start code signals for receiving said data signal and regenerating a clock signal from said information bits;

converting means connected to said clock signal regenerating means and responsive to said start code signals for receiving said data signal and converting said SPL information codes to NRZ information codes;

counting clock signal generating means for generating a counting clock signal having a frequency higher than the frequency of said information bits;

selection means for selecting the plurality of information bits of one of said codes;

counting means connected to said clock signal generating means for counting said counting clock signal in a first direction when the level of the information bit selected by said selection means is at a predetermined first level and in a second direction when the information bit selected by said selection means is at a predetermined second level to produce a counting result, said counting means counting in said first and second direction at the same rate; and

signal reproducing means for reproducing said data signal according to said counting result of said counting means.

2. A system for detecting and recovering the information encoded in a data signal according to claim 1 wherein said counting clock signal generating means generates a counting signal whose frequency is dependent on the signal power level of each portion of each bit of said signal.

3. A system for detecting and recovering the information encoded in a data signal according to claim 1 wherein said counting means is an up-down counter which counts up said clock counting signal when the level of a selected said information bit is a logic "H" and counts down said clock counting signal when the level of a selected said information bit is a logic "L".

4. A system for detecting and recovering the information encoded in a data signal according to claim 1 wherein said counting means is a bi-directional shift register which shifts to the right in response to said counting signal when the level of a selected said information bit is a logic "H" and shifts to the left when a said selected information bit is a logic "L".