Complementary MOS field effect transistor integrated circuit with protection function

• US 4,607,274 A
• Filed: 10/17/1983
• Issued: 08/19/1986
• Est. Priority Date: 10/15/1982
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yoshitake, Kazuki
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Henn, Terri M.
• Application Number:
  US06/542,369
• Time in Patent Office: 1,037 Days
• Field of Search: 357/42, 357/41, 357/13
• US Class Current: 257/357
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

This invention provides a structure for preventing input part and/or an output part of the semiconductor chip forming complementary MOS field effect transistors from being damaged by accumulated static charges, wherein regions of the conductivity types as and higher impurity concentrations than a semiconductor substrate and a well region, respectively, are formed at the respective surfaces to come in contact with each other such that diodes be formed and the diodes are connected to an electrode pad.

Claims

1. A complementary field effect transistor comprising a semiconductor substrate of one conductivity type, a first region of another conductivity type formed in said semiconductor substrate, a first type field effect transistor formed on said semiconductor substrate, a second type field effect transistor formed on said first region, each of said first and second types of field effect transistors having a source region, a drain region and a channel region located therebetween, gate electrodes formed on said channel regions of said first and second type field effect transistors through an insulating film, a second region of said one conductivity type having a high impurity concentration, said second region being formed in the surface area of said semiconductor substrate, said second region having a side which comes into contact with said drain region of said first type field effect transistor to form a first diode therebetween, a third region of said other conductivity type having a high impurity concentration, said third region being formed in the surface area of said first region to come in contact with said drain region of said second type field effect transistor to form a second diode therebetween, said second region and said third region being in contact with each other to form a third diode therebetween an output wiring layer connecting the drain regions of said first type and second type field effect transistors, an output electrode pad connected to said output wiring layer, a first power terminal connected to the surface area of said semiconductor substrate at a location that is on one side of said first region which is opposite the side of said first region where said first diode is formed, a second power terminal connected to the surface area of said first region, said first and second diodes being connected in series between said first and second power terminals, said third diode being connected between said first and second power terminals in parallel with the series connection of said first and second diodes, a fourth region of said other conductivity type having an elongated shape to provide a resistor region formed on the surface of said semiconductor substrate to come into contact with said second region to form a fourth diode therebetween, a fifth region of said one conductivity type formed on the surface of said first region to come into contact with said third region to form a fifth diode therebetween, said fourth and fifth diodes being connected in series between said first and second power terminals, an input wiring layer connecting one end of said fourth region and said fifth region, an input electrode pad connected to said input wiring layer, and an additional wiring layer connected to the other end of said fourth region and further connected in common to said gate electrodes of said first and second type field effect transistors.