Vertical type MOS transistor

• US 4,608,584 A
• Filed: 06/13/1984
• Issued: 08/26/1986
• Est. Priority Date: 06/13/1983
• Status: Expired due to Term

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Mihara, Teruyoshi
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/620,290
• Time in Patent Office: 804 Days
• Field of Search: 357/23.4, 357/23.11, 357/55
• US Class Current: 257/336
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The vertical type MOS transistor includes a transistor body region which consists of an N⁺ type (high concentration N type) substrate having a drain electrode connected on its bottom surface, and an N^- type (low concentration N type) layer epitaxially grown on the top surface of the substrate, and a plurality of P type well regions formed with a prescribed interval on the top surface of the N^- type layer. Within a P type well region, there are provided N⁺ type source regions, and an oxidized gate region and a gate electrode that bestride over both of an N⁺ source region and the N^- type drain region which is to function as the effective drain region.

There are provided stopper grooves of dug-out form, situated between and at equal distances from the adjacent P type well regions, extending downward from the surface of the N^- type drain region parallel to the sides of the P type well regions.

Claims

1. A vertical type MOS transistor comprising:

a semiconductor substrate of a first conductivity type;

an upper region formed on the upper surface of the substrate in which are formed a source region of the first conductivity type, a well region of the second conductivity type opposite to the first conductivity type and a drain region of the first conductivity type, said source region, well region and drain region having portions thereof lying along a flat top surface of the upper region, the well region having a side perpendicular to said top surface and forming a channel region between the source and drain regions;

a stopper groove formed in the drain region spaced from and having no portion thereof in contact with the well region so that the flat top surface is interrupted by the groove;

a source electrode electrically connected to the source region;

a gate electrode formed on the channel region through an insulator film; and

a drain electrode formed on the lower surface of the substrate.

2. A vertical type MOS transistor as claimed in claim 1, in which said stopper groove extends downward from said top surface of said upper region parallel to the side of said well region.

3. A vertical type MOS transistor as claimed in claim 1, in which a portion of the bottom side of a gate electrode is embedded into the stopper groove through the intermediary of an oxidized gate layer.