Modular computer system

• US 4,608,631 A
• Filed: 11/19/1984
• Issued: 08/26/1986
• Est. Priority Date: 09/03/1982
• Status: Expired due to Term

• Current Assignee: Radisys Corporation (Reliance Industries Limited)
• Original Assignee: Sequoia Systems, Inc. (Reliance Industries Limited)
• Inventors: Stiffler, Jack J., Nolan, James M. Jr., Wallace, David A., Budwey, Michael J., Karp, Richard A.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/672,799
• Time in Patent Office: 645 Days
• Field of Search: 364/200 MS File, 364/200
• US Class Current: 710/113
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00

Abstract

A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas.

The transfer of the supervisor function from processor to processor is performed by registering the supervisor'"'"'s identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors.

Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.

Claims

1. A computer system comprising,

a plurality of processing elements for simultaneously performing data processing calculations for a plurality of data processing tasks, each of said processing elements performing data processing calculations for one data processing task independently from other data processing elements, said processing element generating request signals;

a common memory area having a plurality of storage locations, each of said plurality of storage locations being accessible by all of said processing elements;

a system bus for transferring signals between said processing elements and said memory area;

at least one processor bus connected to at least one of said plurality of processing elements; and

first arbitration means responsive to request signals generated from at least one of said processing elements for selectively transferring signals between said processor bus and said system bus.

2. A computer system in accordance with claim 1 wherein said first arbitration means further comprises means responsive to said processor request signals for selecting one of said processors.

3. A computer system in accordance with claim 1 wherein said first arbitration means further comprises means responsive to said processor request signals for transferring data signals between said one selected processor and said system bus.

4. A computer system in accordance with claim 1 wherein said common memory area is comprised of a plurality of separate memory elements and said computer system further comprises at least one memory bus connected to at least one of said plurality of memory elements.

5. A computer system in accordance with claim 1 wherein said first arbitration means further comprises means responsive to said processor request signals for transferring address signals selecting one of said memories between said one selected processor and said system bus.

6. A computer system in accordance with claim 5 further comprising slave interface means responsive to said address signals for transferring data between said system bus and said one selected memory.

7. A computer system in accordance with claim 6 wherein each of said memory elements comprises means for generating interrupt signals indicating a fault situtation and said slave interface comprises means responsive to said interrupt signals for generating a service request interrupt signal and means responsive to said interrupt signals for selecting one of said plurality of memory elements.

8. A computer system in accordance with claim 1 further comprising second arbitration means controlled by said first arbitration means for selectively transferring control signals between said memory bus and said system bus.

9. A computer system in accordance with claim 8 wherein said second arbitration means comprises a plurality of slave interfaces, each of said plurality of slave interfaces being connected to one of said plurality of memory buses.

10. A computer system in accordance with claim 9 wherein said first arbitration means comprises means responsive to service request interrupt signals generated by said plurality of slave interfaces for selecting one of said slave interfaces to transfer signals from a selected memory element to said system bus and means for transferring signals from the memory bus connected to said selected memory element to said system bus.

11. A computer system in accordance with claim 9 wherein said first arbitration means comprises means responsive to signals on said system bus generated by a selected memory element for transferring said signals on said system bus to said processor bus.

12. A computer system in accordance with claim 1 wherein said common memory area further comprises a plurality of memory buses, each of said plurality of memory buses being connected to at least one of said plurality of memory elements.

13. A computer system in accordance with claim 12 further comprising at least one peripheral element and bus adapter means for connecting said peripheral unit to one of said memory buses.

14. A computer system in accordance with claim 1 further comprising a plurality of processor buses, each of said plurality of processor buses being connected to at least one of said plurality of processors.

15. A computer system comprising,

a plurality of processing elements for simultaneously performing data processing calculations for a plurality of data processing tasks, each of said processing elements performing data processing calculations for one data processing task independently from other data processing elements, said processing element generating request signals;

a plurality of separate memory elements;

at least one memory bus connected to at least one of said plurality of memory elements;

a system bus for transferring signals between said processing elements and one of said plurality of memory elements;

at least one processor bus connected to at least one of said plurality of processing elements; and

first arbitration means responsive to request signals generated from at least one of said processing elements for selecting one of said processors and for selectively transferring signals between said processor bus and said system bus;

slave interface means responsive to said address signals selecting one of said memories, said address signals being by said one selected processor for transferring data between said system bus and said one selected memory.

16. A computer system in accordance with claim 15 wherein each of said memory elements comprises means for generating interrupt signals indicating a fault situation and said slave interface means comprises means responsive to said interrupt signals for generating a service request interrupt signal and means responsive to said interrupt signals for selecting one of said plurality of memory elements.

17. A computer system in accordance with claim 16 further comprising second arbitration means controlled by said first arbitration means for selectively transferring control signals between said memory bus and said system bus.

18. A computer system in accordance with claim 17 further comprising a plurality of slave interfaces, each of said plurality of slave interfaces being connected to one of said plurality of memory buses.

19. A computer system in accordance with claim 18 wherein said first arbitration means comprises means responsive to service request interrupt signals generated by said plurality of slave interfaces for selecting one of said slave interfaces to transfer signals from a selected memory element to said system bus and means for transferring signals from the memory bus connected to said selected memory element to said system bus.

20. A computer system in accordance with claim 19 wherein said first arbitration means comprises means responsive to signals on said system bus generated by a selected memory element for transferring said signals on said system bus to said processor bus.

21. A computer system in accordance with claim 20 wherein said common memory area further comprises a plurality of memory buses, each of said plurality of memory buses being connected to at least one of said plurality of memory elements.

22. A computer system in accordance with claim 21 further comprising at least one peripheral element and bus adapter means for connecting said peripheral unit to one of said memory buses.

23. A computer system in accordance with claim 21 wherein said bus adapter means comprises means for generating interrupt signals indicating that said peripheral unit is requesting service.

24. A computer system in accordance with claim 23 further comprising a plurality of processor buses, each of said plurality of processor buses being connected to at least one of said plurality of processors.